1.5-V low supply voltage 43-Gb/s delayed flip-flop circuit

Yasushi Amamiya; Yasuyuki Suzuki; Jin Yamazaki; Akira Fujihara; Shinichi Tanaka; Hikaru Hida

doi:10.1109/gaas.2003.1252387

1.5-V low supply voltage 43-Gb/s delayed flip-flop circuit

Yasushi Amamiya, Yasuyuki Suzuki, Jin Yamazaki, Akira Fujihara, Shinichi Tanaka, Hikaru Hida

Research output: Contribution to conference › Paper › peer-review

15 Citations (Scopus)

Abstract

This paper reports the first low (1.5-V) supply voltage D-F/F able to run at a full rate of over 43 Gb/s. The proposed F/F circuitry incorporates parallel current switching together with inductive peaking, a combination that makes it suitable for over-43-Gb/s operation at a supply voltage as low as 1.5 V. The D-F/F, implemented through an InP-HBT process, provided 43-Gb/s error free operation with a large clock phase margin of 232 degrees. Moreover, the D-F/F produced a well-opened 50-Gb/s eye diagram. Power dissipation (P_diss) of the D-F/F core circuit was reduced to 40 mW, which is less than one-tenth that of our conventional D-F/F. The F/F circuitry should help enable development of a low-P_diss 43-Gb/s full-rate module with a 1.5-V-range supply voltage, which can be seamlessly connected with high-speed CMOS I/O circuits.

Original language	English
Pages	169-172
Number of pages	4
DOIs	https://doi.org/10.1109/gaas.2003.1252387
Publication status	Published - 2003
Event	GaAs IC Symposium IEEE Gallium Arsenide Intergrated Circuit Symposium - San Diego, CA, United States Duration: 2003 Nov 9 → 2003 Nov 12

Conference

Conference	GaAs IC Symposium IEEE Gallium Arsenide Intergrated Circuit Symposium
Country/Territory	United States
City	San Diego, CA
Period	03/11/9 → 03/11/12

Keywords

D-F/F
High speed
InP HBT
Low supply voltage

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/gaas.2003.1252387

Cite this

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title = "1.5-V low supply voltage 43-Gb/s delayed flip-flop circuit",

abstract = "This paper reports the first low (1.5-V) supply voltage D-F/F able to run at a full rate of over 43 Gb/s. The proposed F/F circuitry incorporates parallel current switching together with inductive peaking, a combination that makes it suitable for over-43-Gb/s operation at a supply voltage as low as 1.5 V. The D-F/F, implemented through an InP-HBT process, provided 43-Gb/s error free operation with a large clock phase margin of 232 degrees. Moreover, the D-F/F produced a well-opened 50-Gb/s eye diagram. Power dissipation (Pdiss) of the D-F/F core circuit was reduced to 40 mW, which is less than one-tenth that of our conventional D-F/F. The F/F circuitry should help enable development of a low-Pdiss 43-Gb/s full-rate module with a 1.5-V-range supply voltage, which can be seamlessly connected with high-speed CMOS I/O circuits.",

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author = "Yasushi Amamiya and Yasuyuki Suzuki and Jin Yamazaki and Akira Fujihara and Shinichi Tanaka and Hikaru Hida",

year = "2003",

doi = "10.1109/gaas.2003.1252387",

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T1 - 1.5-V low supply voltage 43-Gb/s delayed flip-flop circuit

AU - Amamiya, Yasushi

AU - Suzuki, Yasuyuki

AU - Yamazaki, Jin

AU - Fujihara, Akira

AU - Tanaka, Shinichi

AU - Hida, Hikaru

PY - 2003

Y1 - 2003

N2 - This paper reports the first low (1.5-V) supply voltage D-F/F able to run at a full rate of over 43 Gb/s. The proposed F/F circuitry incorporates parallel current switching together with inductive peaking, a combination that makes it suitable for over-43-Gb/s operation at a supply voltage as low as 1.5 V. The D-F/F, implemented through an InP-HBT process, provided 43-Gb/s error free operation with a large clock phase margin of 232 degrees. Moreover, the D-F/F produced a well-opened 50-Gb/s eye diagram. Power dissipation (Pdiss) of the D-F/F core circuit was reduced to 40 mW, which is less than one-tenth that of our conventional D-F/F. The F/F circuitry should help enable development of a low-Pdiss 43-Gb/s full-rate module with a 1.5-V-range supply voltage, which can be seamlessly connected with high-speed CMOS I/O circuits.

AB - This paper reports the first low (1.5-V) supply voltage D-F/F able to run at a full rate of over 43 Gb/s. The proposed F/F circuitry incorporates parallel current switching together with inductive peaking, a combination that makes it suitable for over-43-Gb/s operation at a supply voltage as low as 1.5 V. The D-F/F, implemented through an InP-HBT process, provided 43-Gb/s error free operation with a large clock phase margin of 232 degrees. Moreover, the D-F/F produced a well-opened 50-Gb/s eye diagram. Power dissipation (Pdiss) of the D-F/F core circuit was reduced to 40 mW, which is less than one-tenth that of our conventional D-F/F. The F/F circuitry should help enable development of a low-Pdiss 43-Gb/s full-rate module with a 1.5-V-range supply voltage, which can be seamlessly connected with high-speed CMOS I/O circuits.

KW - D-F/F

KW - High speed

KW - InP HBT

KW - Low supply voltage

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ER -

1.5-V low supply voltage 43-Gb/s delayed flip-flop circuit

Abstract

Conference

Keywords

ASJC Scopus subject areas

Access to Document

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