820 pin PGA for ultra large-scale BiCMOS devices

Y. Hiruta, N. Hirano, K. Itoh, K. Kato, Y. Yamaji, Y. Motoyama, J. Ohno, R. Homma, S. Kojima, T. Sudo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)


A high pin count, high performance PGA has been developed for next-generation ASIC devices which apply half micron BiCMOS technology and have a maximum usable gate count of 300k. In view of the advances in CMOS and BiCMOS ULSI technologies, high performance packages are required. This new package has been designed with due consideration of all packages functions. Packages for highend devices need to satisfy the following requirements: high electrical performance, low thermal resistance and high pin count in keeping with easy routing of PWB. The body size of the developed package is 60 × 60 mm2. Surface mount type pin joint was adopted to realize high wiring density of a printed wiring board. This package has 820 pins with 50mil pitch, and 5 rows. A small pin diameter of 0. 2mm and a short pin length of 3.0mm were used for surface mounting. The maximum available bonding pad count of the die is 812 with 80 μm pad pitch. The inner bonding pitch of the package is 90 μm. To achieve the narrow pitch and high pad count of the bonding from the dies to the package, highly accurate TAB technology was applied to die assembly. A fine metallization pitch of 90μm was formed on the ceramic PGA. The thermal resistance from die to air is lower than 1.5°C/W at 1m/s air flow velocity. This low thermal resistance was achieved by a CuW heat spreader equipped with an optimized heat sink. An omnidirectional heat sink was developed which has large heat transfer coefficient at slow air flow. Ultra large-scale BiCMOS devices which have power dissipation of as much as 20W can be housed in this package. Great care was taken with respect to the electrical design of the package. The package keeps flexibility of the signal interface types and matches system requirements. Two power supply voltages for the device are available to apply TTL (CMOS) and ECL interfaces by the layer design. The characteristic impedance was controlled at 60Ω. The electric parameters of the package were quantified. The measured cut-off frequency (-3dB) is kept to 1.25GHz including the TAB lead. Electrical characteristics of the package realize complete transmitted signal form of more than 100MHz.

Original languageEnglish
Title of host publicationProceedings - Electronic Components and Technology Conference
PublisherPubl by IEEE
Number of pages9
ISBN (Print)0780307941
Publication statusPublished - 1993
Externally publishedYes
Event1993 Proceedings of the 43rd Electronic Components and Technology Conference - Orlando, FL, USA
Duration: 1993 Jun 11993 Jun 4

Publication series

NameProceedings - Electronic Components and Technology Conference
ISSN (Print)0569-5503


Other1993 Proceedings of the 43rd Electronic Components and Technology Conference
CityOrlando, FL, USA

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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