A 0.25 μ m inner sidewall-assisted super self-aligned gate heterojunction FET fabricated using all dry-etching technology for low voltage controlled LSIs

The first successful fabrication is reported for a high performance 0.25 μ m T-shaped gate pseudomorphic heterojunction FET without the conventional electron-beam lithography and wet etching technology, which often cause long turn-around times and poor reproducibility and controllability, resulting in big obstacles to producing GaAs LSIs. The novel device structure and fabrication process enables realizing very low power consumption GaAs VLSIs superior to even future Si LSIs, and have the following advantages. (i) 0.25 μ m gate formation by optical (stepper) lithography and anisotropic dry etching for SiO₂ sidewalls, and smaller gate formation by an increase in sidewall thickness. (ii) Stable refractory metal gate electrode with low stress and high reliability. (iii) Low resistance T-shaped gate electrode of refractory and low resistivity multilayer metals. (iv) Small R_s and R_d due to ohmic electrodes self-aligned to T-shaped gate electrode, leading to small current saturation voltage V_dss, indispensable for low supply voltage controlled-LSIs. (v) Low damage dry etching of insulating films using low power magnetron ion etching. (vi) Formation of E/D-FETs with different V_T using selective dry etching of GaAs to AlGaAs. (vii) High reproducibility and uniformity due to all dry etching technology.