A 1. 3 V supply voltage AIGaAs/lnGaAs HJFET SCFL D-FF operating at up to 10 gbps

Masahiro Fujii; Tadashi Maeda; Yasuo Ohno

A 1. 3 V supply voltage AIGaAs/lnGaAs HJFET SCFL D-FF operating at up to 10 gbps

Masahiro Fujii, Tadashi Maeda, Yasuo Ohno

Research output: Contribution to journal › Article › peer-review

Abstract

A high speed and low power consumption SCFL circuit design with low supply voltage is proposed. Focusing on the relationship between logic swing and supply voltage, the lower limit for the supply voltage is presented. Theoretical analysis and circuit simulation indicates that the logic swing needs to be optimized to maintain high average g_m within the swing. An SCFL D-FF fabricated using a 0. 25 μm n-AlGaAs/i-InGaAs HJFET process operates at up to lOGbps with power consumption as low as 19 mW at a supply voltage of 1. 3 V.

Original language	English
Pages (from-to)	512-516
Number of pages	5
Journal	IEICE Transactions on Electronics
Volume	E79-C
Issue number	4
Publication status	Published - 1996
Externally published	Yes

Keywords

D-FF
Gaas
Heterojunction fet
High speed
Logic swing
Low power
Low supply voltage
SCFL

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

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title = "A 1. 3 V supply voltage AIGaAs/lnGaAs HJFET SCFL D-FF operating at up to 10 gbps",

abstract = "A high speed and low power consumption SCFL circuit design with low supply voltage is proposed. Focusing on the relationship between logic swing and supply voltage, the lower limit for the supply voltage is presented. Theoretical analysis and circuit simulation indicates that the logic swing needs to be optimized to maintain high average gm within the swing. An SCFL D-FF fabricated using a 0. 25 μm n-AlGaAs/i-InGaAs HJFET process operates at up to lOGbps with power consumption as low as 19 mW at a supply voltage of 1. 3 V.",

keywords = "D-FF, Gaas, Heterojunction fet, High speed, Logic swing, Low power, Low supply voltage, SCFL",

author = "Masahiro Fujii and Tadashi Maeda and Yasuo Ohno",

year = "1996",

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pages = "512--516",

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T1 - A 1. 3 V supply voltage AIGaAs/lnGaAs HJFET SCFL D-FF operating at up to 10 gbps

AU - Fujii, Masahiro

AU - Maeda, Tadashi

AU - Ohno, Yasuo

PY - 1996

Y1 - 1996

N2 - A high speed and low power consumption SCFL circuit design with low supply voltage is proposed. Focusing on the relationship between logic swing and supply voltage, the lower limit for the supply voltage is presented. Theoretical analysis and circuit simulation indicates that the logic swing needs to be optimized to maintain high average gm within the swing. An SCFL D-FF fabricated using a 0. 25 μm n-AlGaAs/i-InGaAs HJFET process operates at up to lOGbps with power consumption as low as 19 mW at a supply voltage of 1. 3 V.

AB - A high speed and low power consumption SCFL circuit design with low supply voltage is proposed. Focusing on the relationship between logic swing and supply voltage, the lower limit for the supply voltage is presented. Theoretical analysis and circuit simulation indicates that the logic swing needs to be optimized to maintain high average gm within the swing. An SCFL D-FF fabricated using a 0. 25 μm n-AlGaAs/i-InGaAs HJFET process operates at up to lOGbps with power consumption as low as 19 mW at a supply voltage of 1. 3 V.

KW - D-FF

KW - Gaas

KW - Heterojunction fet

KW - High speed

KW - Logic swing

KW - Low power

KW - Low supply voltage

KW - SCFL

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SN - 0916-8524

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JO - IEICE Transactions on Electronics

JF - IEICE Transactions on Electronics

IS - 4

ER -

A 1. 3 V supply voltage AIGaAs/lnGaAs HJFET SCFL D-FF operating at up to 10 gbps

Abstract

Keywords

ASJC Scopus subject areas

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