A 40 nm 2 kb MTJ-Based Non-Volatile SRAM Macro with Novel Data-Aware Store Architecture for Normally Off Computing

Kenta Suzuki, Keizo Hiraga, Kazuhiro Bessho, Kimiyoshi Usami, Taku Umebayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We propose a magnetic tunnel junction (MTJ)-based nonvolatile SRAM (NVSRAM) to obtain normally off computing. The proposed NVSRAM not only combines SRAM performance and non-volatility but also shows improved area efficiency by sharing the driver with peripheral circuits. Moreover, the data-aware store scheme enables reduction in store energy by data comparison control and a verify operation that mitigates MTJ process variation. We fabricated a 2 kb macro by using a 40 nm process with optimized memory cells to overcome the risk of latch destruction of conventional cells. The measurement results demonstrated a non-volatile function and 3.5x store energy reduction by the store control optimization.

Original languageEnglish
Title of host publication2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9784863488069
DOIs
Publication statusPublished - 2023
Event2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 - Kyoto, Japan
Duration: 2023 Jun 112023 Jun 16

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2023-June
ISSN (Print)0743-1562

Conference

Conference2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
Country/TerritoryJapan
CityKyoto
Period23/6/1123/6/16

Keywords

  • MTJ
  • Non-volatile SRAM
  • Non-volatile flip-flop
  • Normally off computing
  • Power gating
  • STT-MRAM

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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