A Fine-grain Dynamic Sleep Control Scheme in MIPS R3000

Naomi Seki; Lei Zhao; Jo Kei; Daisuke Ikebuchi; Yu Kojima; Yohei Hasegawa; Hideharu Amano; Kashima Toshihiro Kashima; Seidai Takeda; Toshiaki Shirai; Mitustaka Nakata; Kimiyoshi Usami; Tetsuya Sunata; Jun Kanai; Mitaro Namiki; Masaaki Kondo; Hiroshi Nakamura

doi:10.1109/ICCD.2008.4751924

A Fine-grain Dynamic Sleep Control Scheme in MIPS R3000

Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Kashima Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitustaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

36 Citations (Scopus)

Abstract

A fine-grain dynamic power gating is proposed for saving the leakage power in MIPS R3000 by sleep control and applied to a processor pipeline. An execution unit is divided into four small units: multiplier, divider, shifter and other (CLU). The power of each unit is cut off dynamically, based on the operation. We tape-outed the prototype chip Geyser-0, which provides an R3000 Core with the power reduction technique, 16 KB caches and Translation Lookaside Buffer (TLB) using 90 nm CMOS technology. The evaluation results of four benchmark programs for embedded applications show that 47% of the leakage power is reduced on average with 41% area overhead.

Original language	English
Title of host publication	26th IEEE International Conference on Computer Design 2008, ICCD
Pages	612-617
Number of pages	6
DOIs	https://doi.org/10.1109/ICCD.2008.4751924
Publication status	Published - 2008
Event	26th IEEE International Conference on Computer Design 2008, ICCD - Lake Tahoe, CA, United States Duration: 2008 Oct 12 → 2008 Oct 15

Publication series

Name	26th IEEE International Conference on Computer Design 2008, ICCD

Conference

Conference	26th IEEE International Conference on Computer Design 2008, ICCD
Country/Territory	United States
City	Lake Tahoe, CA
Period	08/10/12 → 08/10/15

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ICCD.2008.4751924

Cite this

Seki, N., Zhao, L., Kei, J., Ikebuchi, D., Kojima, Y., Hasegawa, Y., Amano, H., Toshihiro Kashima, K., Takeda, S., Shirai, T., Nakata, M., Usami, K., Sunata, T., Kanai, J., Namiki, M., Kondo, M., & Nakamura, H. (2008). A Fine-grain Dynamic Sleep Control Scheme in MIPS R3000. In 26th IEEE International Conference on Computer Design 2008, ICCD (pp. 612-617). [4751924] (26th IEEE International Conference on Computer Design 2008, ICCD). https://doi.org/10.1109/ICCD.2008.4751924

Seki, N, Zhao, L, Kei, J, Ikebuchi, D, Kojima, Y, Hasegawa, Y, Amano, H, Toshihiro Kashima, K, Takeda, S, Shirai, T, Nakata, M, Usami, K, Sunata, T, Kanai, J, Namiki, M, Kondo, M & Nakamura, H 2008, A Fine-grain Dynamic Sleep Control Scheme in MIPS R3000. in 26th IEEE International Conference on Computer Design 2008, ICCD., 4751924, 26th IEEE International Conference on Computer Design 2008, ICCD, pp. 612-617, 26th IEEE International Conference on Computer Design 2008, ICCD, Lake Tahoe, CA, United States, 08/10/12. https://doi.org/10.1109/ICCD.2008.4751924

@inproceedings{1bb80416a0234dbd9b61f58d98bdb33b,

title = "A Fine-grain Dynamic Sleep Control Scheme in MIPS R3000",

abstract = "A fine-grain dynamic power gating is proposed for saving the leakage power in MIPS R3000 by sleep control and applied to a processor pipeline. An execution unit is divided into four small units: multiplier, divider, shifter and other (CLU). The power of each unit is cut off dynamically, based on the operation. We tape-outed the prototype chip Geyser-0, which provides an R3000 Core with the power reduction technique, 16 KB caches and Translation Lookaside Buffer (TLB) using 90 nm CMOS technology. The evaluation results of four benchmark programs for embedded applications show that 47% of the leakage power is reduced on average with 41% area overhead.",

author = "Naomi Seki and Lei Zhao and Jo Kei and Daisuke Ikebuchi and Yu Kojima and Yohei Hasegawa and Hideharu Amano and {Toshihiro Kashima}, Kashima and Seidai Takeda and Toshiaki Shirai and Mitustaka Nakata and Kimiyoshi Usami and Tetsuya Sunata and Jun Kanai and Mitaro Namiki and Masaaki Kondo and Hiroshi Nakamura",

year = "2008",

doi = "10.1109/ICCD.2008.4751924",

language = "English",

isbn = "9781424426584",

series = "26th IEEE International Conference on Computer Design 2008, ICCD",

pages = "612--617",

booktitle = "26th IEEE International Conference on Computer Design 2008, ICCD",

note = "26th IEEE International Conference on Computer Design 2008, ICCD ; Conference date: 12-10-2008 Through 15-10-2008",

}

TY - GEN

T1 - A Fine-grain Dynamic Sleep Control Scheme in MIPS R3000

AU - Seki, Naomi

AU - Zhao, Lei

AU - Kei, Jo

AU - Ikebuchi, Daisuke

AU - Kojima, Yu

AU - Hasegawa, Yohei

AU - Amano, Hideharu

AU - Toshihiro Kashima, Kashima

AU - Takeda, Seidai

AU - Shirai, Toshiaki

AU - Nakata, Mitustaka

AU - Usami, Kimiyoshi

AU - Sunata, Tetsuya

AU - Kanai, Jun

AU - Namiki, Mitaro

AU - Kondo, Masaaki

AU - Nakamura, Hiroshi

PY - 2008

Y1 - 2008

N2 - A fine-grain dynamic power gating is proposed for saving the leakage power in MIPS R3000 by sleep control and applied to a processor pipeline. An execution unit is divided into four small units: multiplier, divider, shifter and other (CLU). The power of each unit is cut off dynamically, based on the operation. We tape-outed the prototype chip Geyser-0, which provides an R3000 Core with the power reduction technique, 16 KB caches and Translation Lookaside Buffer (TLB) using 90 nm CMOS technology. The evaluation results of four benchmark programs for embedded applications show that 47% of the leakage power is reduced on average with 41% area overhead.

AB - A fine-grain dynamic power gating is proposed for saving the leakage power in MIPS R3000 by sleep control and applied to a processor pipeline. An execution unit is divided into four small units: multiplier, divider, shifter and other (CLU). The power of each unit is cut off dynamically, based on the operation. We tape-outed the prototype chip Geyser-0, which provides an R3000 Core with the power reduction technique, 16 KB caches and Translation Lookaside Buffer (TLB) using 90 nm CMOS technology. The evaluation results of four benchmark programs for embedded applications show that 47% of the leakage power is reduced on average with 41% area overhead.

UR - http://www.scopus.com/inward/record.url?scp=62349102732&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=62349102732&partnerID=8YFLogxK

U2 - 10.1109/ICCD.2008.4751924

DO - 10.1109/ICCD.2008.4751924

M3 - Conference contribution

AN - SCOPUS:62349102732

SN - 9781424426584

T3 - 26th IEEE International Conference on Computer Design 2008, ICCD

SP - 612

EP - 617

BT - 26th IEEE International Conference on Computer Design 2008, ICCD

T2 - 26th IEEE International Conference on Computer Design 2008, ICCD

Y2 - 12 October 2008 through 15 October 2008

ER -

A Fine-grain Dynamic Sleep Control Scheme in MIPS R3000

Abstract

Publication series

Conference

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this