A multi-Vdd dynamic variable-pipeline on-chip router for CMPs

Hiroki Matsutani; Yuto Hirata; Michihiro Koibuchi; Kimiyoshi Usami; Hiroshi Nakamura; Hideharu Amano

doi:10.1109/ASPDAC.2012.6164982

A multi-Vdd dynamic variable-pipeline on-chip router for CMPs

Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

16 Citations (Scopus)

Abstract

We propose a multi-voltage (multi-Vdd) variable pipeline router to reduce the power consumption of Network-on-Chips (NoCs) designed for chip multi-processors (CMPs). Our multi-Vdd variable pipeline router adjusts its pipeline depth (i.e., communication latency) and supply voltage level in response to the applied workload. Unlike dynamic voltage and frequency scaling (DVFS) routers, the operating frequency is the same for all routers throughout the CMP; thus, there is no need to synchronize neighboring routers working at different frequencies. In this paper, we implemented the multi-Vdd variable pipeline router, which selects two supply voltage levels and pipeline modes, using a 65nm CMOS process and evaluated it using a full-system CMP simulator. Evaluation results show that although the application performance degraded by 1.0% to 2.1%, the standby power of NoCs reduced by 10.4% to 44.4%.

Original language	English
Title of host publication	ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference
Pages	407-412
Number of pages	6
DOIs	https://doi.org/10.1109/ASPDAC.2012.6164982
Publication status	Published - 2012
Event	17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012 - Sydney, NSW, Australia Duration: 2012 Jan 30 → 2012 Feb 2

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Conference

Conference	17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012
Country/Territory	Australia
City	Sydney, NSW
Period	12/1/30 → 12/2/2

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1109/ASPDAC.2012.6164982

Cite this

Matsutani, H., Hirata, Y., Koibuchi, M., Usami, K., Nakamura, H., & Amano, H. (2012). A multi-Vdd dynamic variable-pipeline on-chip router for CMPs. In ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference (pp. 407-412). Article 6164982 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2012.6164982

A multi-Vdd dynamic variable-pipeline on-chip router for CMPs. / Matsutani, Hiroki; Hirata, Yuto; Koibuchi, Michihiro et al.
ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference. 2012. p. 407-412 6164982 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Matsutani, H, Hirata, Y, Koibuchi, M, Usami, K, Nakamura, H & Amano, H 2012, A multi-Vdd dynamic variable-pipeline on-chip router for CMPs. in ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference., 6164982, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 407-412, 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, NSW, Australia, 12/1/30. https://doi.org/10.1109/ASPDAC.2012.6164982

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abstract = "We propose a multi-voltage (multi-Vdd) variable pipeline router to reduce the power consumption of Network-on-Chips (NoCs) designed for chip multi-processors (CMPs). Our multi-Vdd variable pipeline router adjusts its pipeline depth (i.e., communication latency) and supply voltage level in response to the applied workload. Unlike dynamic voltage and frequency scaling (DVFS) routers, the operating frequency is the same for all routers throughout the CMP; thus, there is no need to synchronize neighboring routers working at different frequencies. In this paper, we implemented the multi-Vdd variable pipeline router, which selects two supply voltage levels and pipeline modes, using a 65nm CMOS process and evaluated it using a full-system CMP simulator. Evaluation results show that although the application performance degraded by 1.0% to 2.1%, the standby power of NoCs reduced by 10.4% to 44.4%.",

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A multi-Vdd dynamic variable-pipeline on-chip router for CMPs

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