TY - GEN
T1 - A scalable 3D heterogeneous multi-core processor with inductive-coupling ThruChip interface
AU - Miura, Noriyuki
AU - Koizumi, Yusuke
AU - Sasaki, Eiichi
AU - Take, Yasuhiro
AU - Matsutani, Hiroki
AU - Kuroda, Tadahir
AU - Amano, Hideharu
AU - Sakamoto, Ryuichi
AU - Namiki, Mitaro
AU - Usami, Kimiyoshi
AU - Kondo, Masaaki
AU - Nakamura, Hiroshi
PY - 2013/8/15
Y1 - 2013/8/15
N2 - A scalable heterogeneous multi-core processor is developed. 3D heterogeneous chip stacking of a general-purpose CPU and reconfigurable multi-core accelerators improves computational energy efficiency by proper task assignment and massive parallel computing. The stacked chips interconnect through a scalable 3D Network on Chip (NoC). By simply changing the number of stacked accelerator chips, processor parallelism can be widely scaled. In combination with Dynamic Voltage and Frequency Scaling (DVFS), the energy efficiency can be optimized for various performance requirements. No design change is needed, and hence no additional Non-Recurring Engineering (NRE) cost. An inductive-coupling ThruChip Interface (TCI) is applied to stacked-chip communications, forming a low-cost and robust high-speed 3D NoC. A prototype demonstration system has been developed with 65nm CMOS test chips. Successful system operations including lO-hours continuous Linux OS operation are confirmed for the first time.
AB - A scalable heterogeneous multi-core processor is developed. 3D heterogeneous chip stacking of a general-purpose CPU and reconfigurable multi-core accelerators improves computational energy efficiency by proper task assignment and massive parallel computing. The stacked chips interconnect through a scalable 3D Network on Chip (NoC). By simply changing the number of stacked accelerator chips, processor parallelism can be widely scaled. In combination with Dynamic Voltage and Frequency Scaling (DVFS), the energy efficiency can be optimized for various performance requirements. No design change is needed, and hence no additional Non-Recurring Engineering (NRE) cost. An inductive-coupling ThruChip Interface (TCI) is applied to stacked-chip communications, forming a low-cost and robust high-speed 3D NoC. A prototype demonstration system has been developed with 65nm CMOS test chips. Successful system operations including lO-hours continuous Linux OS operation are confirmed for the first time.
UR - http://www.scopus.com/inward/record.url?scp=84881323839&partnerID=8YFLogxK
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U2 - 10.1109/CoolChips.2013.6547916
DO - 10.1109/CoolChips.2013.6547916
M3 - Conference contribution
AN - SCOPUS:84881323839
SN - 9781467357814
T3 - IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI
BT - IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI
T2 - 16th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2013
Y2 - 17 April 2013 through 19 April 2013
ER -