A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface

Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Recent battery driven IT devices including smart phone and tablets require versatile functions and high performance with low energy consumption. On the other hand, the initial cost of LSI for design and mask development has increased rapidly, and development of an SoC (System-on-a Chip) for each product has become difficult. Although flexible reconfigurable architectures can be a solution, the performance scalability is also necessary to cope with the wide performance range of products. As a solution, heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect is proposed. This system consists of a MIPS-R3000 compatible embedded CPU and reconfigurable accelerators. Since chips are connected with wireless inductive coupling channels, the number and types of accelerators can be tailored easily depending on the requirement of the product.

Original languageEnglish
Title of host publication2013 IEEE Hot Chips 25 Symposium, HCS 2013
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467388818
DOIs
Publication statusPublished - 2013 May 24
Event25th IEEE Hot Chips Symposium, HCS 2013 - Stanford, United States
Duration: 2013 Aug 252013 Aug 27

Publication series

Name2013 IEEE Hot Chips 25 Symposium, HCS 2013

Other

Other25th IEEE Hot Chips Symposium, HCS 2013
Country/TerritoryUnited States
CityStanford
Period13/8/2513/8/27

ASJC Scopus subject areas

  • Hardware and Architecture

Fingerprint

Dive into the research topics of 'A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface'. Together they form a unique fingerprint.

Cite this