An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages

Shin Ya Abe; Youhua Shi; Kimiyoshi Usami; Masao Yanagisawa; Nozomu Togawa

doi:10.1109/VLDI-DAT.2013.6533808

An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages

Shin Ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, we propose an adaptive voltage huddle-based distributed-register architecture (AVHDR architecture) that integrates dynamic multiple supply voltages and interconnection delays into high-level synthesis. Next, we propose a high-level synthesis algorithm for AVHDR architectures. Our algorithm is based on iterative improvement of scheduling/binding and floorplanning. In the iteration process, huddles, each of which abstracts modules placed close to each other, are naturally generated using floorplanning. Low-supply voltages are assigned to non-critical operations, and leakage power is cut off by turning off the power supply to the sleeping functional units. Experimental results show that our algorithm achieves 50% energy-saving compared with conventional algorithms.

Original language	English
Title of host publication	2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
DOIs	https://doi.org/10.1109/VLDI-DAT.2013.6533808
Publication status	Published - 2013 Aug 15
Event	2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 - Hsinchu, Taiwan, Province of China Duration: 2013 Apr 22 → 2013 Apr 24

Publication series

Name	2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013

Conference

Conference	2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	13/4/22 → 13/4/24

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/VLDI-DAT.2013.6533808

Cite this

Abe, S. Y., Shi, Y., Usami, K., Yanagisawa, M., & Togawa, N. (2013). An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages. In 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 [6533808] (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013). https://doi.org/10.1109/VLDI-DAT.2013.6533808

An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages. / Abe, Shin Ya; Shi, Youhua; Usami, Kimiyoshi et al.
2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 2013. 6533808 (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abe, SY, Shi, Y, Usami, K, Yanagisawa, M & Togawa, N 2013, An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages. in 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013., 6533808, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013, Hsinchu, Taiwan, Province of China, 13/4/22. https://doi.org/10.1109/VLDI-DAT.2013.6533808

Abe SY, Shi Y, Usami K, Yanagisawa M, Togawa N. An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages. In 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 2013. 6533808. (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013). doi: 10.1109/VLDI-DAT.2013.6533808

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title = "An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages",

abstract = "In this paper, we propose an adaptive voltage huddle-based distributed-register architecture (AVHDR architecture) that integrates dynamic multiple supply voltages and interconnection delays into high-level synthesis. Next, we propose a high-level synthesis algorithm for AVHDR architectures. Our algorithm is based on iterative improvement of scheduling/binding and floorplanning. In the iteration process, huddles, each of which abstracts modules placed close to each other, are naturally generated using floorplanning. Low-supply voltages are assigned to non-critical operations, and leakage power is cut off by turning off the power supply to the sleeping functional units. Experimental results show that our algorithm achieves 50% energy-saving compared with conventional algorithms.",

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AB - In this paper, we propose an adaptive voltage huddle-based distributed-register architecture (AVHDR architecture) that integrates dynamic multiple supply voltages and interconnection delays into high-level synthesis. Next, we propose a high-level synthesis algorithm for AVHDR architectures. Our algorithm is based on iterative improvement of scheduling/binding and floorplanning. In the iteration process, huddles, each of which abstracts modules placed close to each other, are naturally generated using floorplanning. Low-supply voltages are assigned to non-critical operations, and leakage power is cut off by turning off the power supply to the sleeping functional units. Experimental results show that our algorithm achieves 50% energy-saving compared with conventional algorithms.

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An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages

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