Buffer-trapping effects on drain lag and power compression in GaN FET

Buffer-trapping effects in a GaN MESFET are studied by two-dimensional transient simulation. A three-level compensation model is adopted for a semi-insulating buffer layer where a shallow donor, a deep donor and a deep acceptor are considered. It is shown that when the drain voltage VD is raised, the drain current overshoots the steady-state value, and when V_D is lowered, the drain current remains at a low value for some periods, showing drain lag behavior. This drain lag is shown to become a cause of so-called power compression in the GaN MESFET.