Chip-level performance maximization using ASIS (Application-specific Interconnect Structure) wiring design concept for 45 nm CMOS devices

N. Oda; H. Imura; N. Kawahara; M. Tagami; H. Kunishima; S. Sone; S. Ohnishi; K. Yamada; Y. Kakuhara; M. Sekine; Y. Hayashi; K. Ueno

Chip-level performance maximization using ASIS (Application-specific Interconnect Structure) wiring design concept for 45 nm CMOS devices

N. Oda, H. Imura, N. Kawahara, M. Tagami, H. Kunishima, S. Sone, S. Ohnishi, K. Yamada, Y. Kakuhara, M. Sekine, Y. Hayashi, K. Ueno

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A novel interconnect design concept named "ASIS (Application-specific Interconnect Structure)" is presented for 45 nm CMOS performance maximization. Basic scheme of ASIS is that corresponding to applications, such as high-performance, low-power or high reliability, interconnect structure as well as metal thickness is individually optimized in order to maximize chip-level performance matched to the application. Our investigation shows that for low power application, the increased resistivity of scaled-down Cu-wire is not a main issue, so that thinner wire is more advantageous. For high-performance application, partially double pitch structure for local and intermediate layers is advantageous. For high-reliability requirement, CuAl-alloy or CoWP cap-metal is quite effective for boosting reliability.

Original language	English
Title of host publication	IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest
Pages	1022-1025
Number of pages	4
Publication status	Published - 2005
Externally published	Yes
Event	IEEE International Electron Devices Meeting, 2005 IEDM - Washington, DC, MD, United States Duration: 2005 Dec 5 → 2005 Dec 7

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Volume	2005
ISSN (Print)	0163-1918

Conference

Conference	IEEE International Electron Devices Meeting, 2005 IEDM
Country/Territory	United States
City	Washington, DC, MD
Period	05/12/5 → 05/12/7

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Cite this

Oda, N., Imura, H., Kawahara, N., Tagami, M., Kunishima, H., Sone, S., Ohnishi, S., Yamada, K., Kakuhara, Y., Sekine, M., Hayashi, Y., & Ueno, K. (2005). Chip-level performance maximization using ASIS (Application-specific Interconnect Structure) wiring design concept for 45 nm CMOS devices. In IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest (pp. 1022-1025). [1609538] (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2005).

Chip-level performance maximization using ASIS (Application-specific Interconnect Structure) wiring design concept for 45 nm CMOS devices. / Oda, N.; Imura, H.; Kawahara, N. et al.
IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest. 2005. p. 1022-1025 1609538 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Oda, N, Imura, H, Kawahara, N, Tagami, M, Kunishima, H, Sone, S, Ohnishi, S, Yamada, K, Kakuhara, Y, Sekine, M, Hayashi, Y & Ueno, K 2005, Chip-level performance maximization using ASIS (Application-specific Interconnect Structure) wiring design concept for 45 nm CMOS devices. in IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest., 1609538, Technical Digest - International Electron Devices Meeting, IEDM, vol. 2005, pp. 1022-1025, IEEE International Electron Devices Meeting, 2005 IEDM, Washington, DC, MD, United States, 05/12/5.

Oda N, Imura H, Kawahara N, Tagami M, Kunishima H, Sone S et al. Chip-level performance maximization using ASIS (Application-specific Interconnect Structure) wiring design concept for 45 nm CMOS devices. In IEEE International Electron Devices Meeting, 2005 IEDM - Technical Digest. 2005. p. 1022-1025. 1609538. (Technical Digest - International Electron Devices Meeting, IEDM).

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abstract = "A novel interconnect design concept named {"}ASIS (Application-specific Interconnect Structure){"} is presented for 45 nm CMOS performance maximization. Basic scheme of ASIS is that corresponding to applications, such as high-performance, low-power or high reliability, interconnect structure as well as metal thickness is individually optimized in order to maximize chip-level performance matched to the application. Our investigation shows that for low power application, the increased resistivity of scaled-down Cu-wire is not a main issue, so that thinner wire is more advantageous. For high-performance application, partially double pitch structure for local and intermediate layers is advantageous. For high-reliability requirement, CuAl-alloy or CoWP cap-metal is quite effective for boosting reliability.",

author = "N. Oda and H. Imura and N. Kawahara and M. Tagami and H. Kunishima and S. Sone and S. Ohnishi and K. Yamada and Y. Kakuhara and M. Sekine and Y. Hayashi and K. Ueno",

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AU - Kunishima, H.

AU - Sone, S.

AU - Ohnishi, S.

AU - Yamada, K.

AU - Kakuhara, Y.

AU - Sekine, M.

AU - Hayashi, Y.

AU - Ueno, K.

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AB - A novel interconnect design concept named "ASIS (Application-specific Interconnect Structure)" is presented for 45 nm CMOS performance maximization. Basic scheme of ASIS is that corresponding to applications, such as high-performance, low-power or high reliability, interconnect structure as well as metal thickness is individually optimized in order to maximize chip-level performance matched to the application. Our investigation shows that for low power application, the increased resistivity of scaled-down Cu-wire is not a main issue, so that thinner wire is more advantageous. For high-performance application, partially double pitch structure for local and intermediate layers is advantageous. For high-reliability requirement, CuAl-alloy or CoWP cap-metal is quite effective for boosting reliability.

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Chip-level performance maximization using ASIS (Application-specific Interconnect Structure) wiring design concept for 45 nm CMOS devices

Abstract

Publication series

Conference

ASJC Scopus subject areas

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