Chip-level performance maximization using ASIS (Application-specific Interconnect Structure) wiring design concept for 45 nm CMOS devices
N. Oda, H. Imura, N. Kawahara, M. Tagami, H. Kunishima, S. Sone, S. Ohnishi, K. Yamada, Y. Kakuhara, M. Sekine, Y. Hayashi, K. Ueno
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
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