Chip-level performance maximization using ASIS (Application-specific Interconnect Structure) wiring design concept for 45 nm CMOS devices

N. Oda, H. Imura, N. Kawahara, M. Tagami, H. Kunishima, S. Sone, S. Ohnishi, K. Yamada, Y. Kakuhara, M. Sekine, Y. Hayashi, K. Ueno

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Fingerprint

Dive into the research topics of 'Chip-level performance maximization using ASIS (Application-specific Interconnect Structure) wiring design concept for 45 nm CMOS devices'. Together they form a unique fingerprint.

Keyphrases

Engineering