Chip-level performance maximization using ASIS woring design concept for 45 nm CMOS generation

N. Oda; H. Imura; N. Kawahara; M. Tagami; H. Kunishima; S. Sone; S. Ohnishi; K. Yamada; Y. Kakuhara; M. Sekine; Y. Hayashi; K. Ueno

Chip-level performance maximization using ASIS woring design concept for 45 nm CMOS generation

N. Oda, H. Imura, N. Kawahara, M. Tagami, H. Kunishima, S. Sone, S. Ohnishi, K. Yamada, Y. Kakuhara, M. Sekine, Y. Hayashi, K. Ueno

Functional Control Systems

Research output: Contribution to journal › Article › peer-review

5 Citations (Scopus)

Original language	English
Pages (from-to)	848-855
Journal	IEICE Transaction on Electronics
Volume	E90-C
Publication status	Published - 2007 Apr 15

Cite this

@article{cb954785af6640a8b6e33d4f723b9649,

title = "Chip-level performance maximization using ASIS woring design concept for 45 nm CMOS generation",

author = "N. Oda and H. Imura and N. Kawahara and M. Tagami and H. Kunishima and S. Sone and S. Ohnishi and K. Yamada and Y. Kakuhara and M. Sekine and Y. Hayashi and K. Ueno",

year = "2007",

month = apr,

day = "15",

language = "English",

volume = "E90-C",

pages = "848--855",

journal = "IEICE Transaction on Electronics",

}

TY - JOUR

T1 - Chip-level performance maximization using ASIS woring design concept for 45 nm CMOS generation

AU - Oda, N.

AU - Imura, H.

AU - Kawahara, N.

AU - Tagami, M.

AU - Kunishima, H.

AU - Sone, S.

AU - Ohnishi, S.

AU - Yamada, K.

AU - Kakuhara, Y.

AU - Sekine, M.

AU - Hayashi, Y.

AU - Ueno, K.

PY - 2007/4/15

Y1 - 2007/4/15

M3 - Article

VL - E90-C

SP - 848

EP - 855

JO - IEICE Transaction on Electronics

JF - IEICE Transaction on Electronics

ER -