Delay modeling and static timing analysis for MTCMOS circuits

Naoaki Ohkubo; Kimiyoshi Usami

Delay modeling and static timing analysis for MTCMOS circuits

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology targeting at MTCMOS circuits. In the proposed method, we prepare a delay look-up table (LUT) consisting of the input slew, the output load capacitance, the virtual ground length, and a power-switch size. Using this LUT, we compute a circuit delay for each logic cell by applying the linear interpolation. Experimental results show that the proposed methodology enables to estimate the critical path delay in a good accuracy.

Original language	English
Title of host publication	Proceedings of the ASP-DAC 2006
Subtitle of host publication	Asia and South Pacific Design Automation Conference 2006
Pages	570-575
Number of pages	6
Publication status	Published - 2006 Sept 19
Event	ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 - Yokohama, Japan Duration: 2006 Jan 24 → 2006 Jan 27

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	2006

Conference

Conference	ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006
Country/Territory	Japan
City	Yokohama
Period	06/1/24 → 06/1/27

Keywords

Delay
Interpolation
Leakage power
MTCMOS
Selective-MT
Static timing analysis

ASJC Scopus subject areas

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Cite this

Delay modeling and static timing analysis for MTCMOS circuits. / Ohkubo, Naoaki; Usami, Kimiyoshi.

Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006. 2006. p. 570-575 1594746 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2006).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ohkubo, N & Usami, K 2006, Delay modeling and static timing analysis for MTCMOS circuits. in Proceedings of the ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006., 1594746, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 2006, pp. 570-575, ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006, Yokohama, Japan, 06/1/24.

@inproceedings{5b81b8741ce547bd927bc6fa080f85c0,

title = "Delay modeling and static timing analysis for MTCMOS circuits",

abstract = "One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology targeting at MTCMOS circuits. In the proposed method, we prepare a delay look-up table (LUT) consisting of the input slew, the output load capacitance, the virtual ground length, and a power-switch size. Using this LUT, we compute a circuit delay for each logic cell by applying the linear interpolation. Experimental results show that the proposed methodology enables to estimate the critical path delay in a good accuracy.",

keywords = "Delay, Interpolation, Leakage power, MTCMOS, Selective-MT, Static timing analysis",

author = "Naoaki Ohkubo and Kimiyoshi Usami",

year = "2006",

month = sep,

day = "19",

language = "English",

isbn = "0780394518",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

pages = "570--575",

booktitle = "Proceedings of the ASP-DAC 2006",

note = "ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 ; Conference date: 24-01-2006 Through 27-01-2006",

}

TY - GEN

T1 - Delay modeling and static timing analysis for MTCMOS circuits

AU - Ohkubo, Naoaki

AU - Usami, Kimiyoshi

PY - 2006/9/19

Y1 - 2006/9/19

N2 - One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology targeting at MTCMOS circuits. In the proposed method, we prepare a delay look-up table (LUT) consisting of the input slew, the output load capacitance, the virtual ground length, and a power-switch size. Using this LUT, we compute a circuit delay for each logic cell by applying the linear interpolation. Experimental results show that the proposed methodology enables to estimate the critical path delay in a good accuracy.

AB - One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology targeting at MTCMOS circuits. In the proposed method, we prepare a delay look-up table (LUT) consisting of the input slew, the output load capacitance, the virtual ground length, and a power-switch size. Using this LUT, we compute a circuit delay for each logic cell by applying the linear interpolation. Experimental results show that the proposed methodology enables to estimate the critical path delay in a good accuracy.

KW - Delay

KW - Interpolation

KW - Leakage power

KW - MTCMOS

KW - Selective-MT

KW - Static timing analysis

UR - http://www.scopus.com/inward/record.url?scp=33748588117&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33748588117&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:33748588117

SN - 0780394518

SN - 9780780394513

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 570

EP - 575

BT - Proceedings of the ASP-DAC 2006

T2 - ASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006

Y2 - 24 January 2006 through 27 January 2006

ER -

Delay modeling and static timing analysis for MTCMOS circuits

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Other files and links

Fingerprint

Cite this