Dynamic sleep control for finite-state-machines to reduce active leakage power

Engineering & Materials Science

• Clocks 19%
• Combinatorial circuits 28%
• Degradation 31%
• Finite automata 73%
• Flip flop circuits 26%
• Hot Temperature 10%
• Logic circuits 25%
• Logic gates 26%
• Sleep 71%
• Temperature 9%
• Testing 23%
• Throughput 15%
• Transistors 57%

Mathematics

• Burn-in 29%
• Degradation 23%
• Finite State Machine 89%
• Flip 10%
• Leakage 88%
• Logic 15%
• Performance 5%
• Simulation 6%
• Sleep 100%
• State Transition 12%
• Testing 13%
• Throughput 12%