TY - GEN
T1 - Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application
AU - Usami, Kimiyoshi
AU - Akaike, Junya
AU - Akiba, Sosuke
AU - Kudo, Masaru
AU - Amano, Hideharu
AU - Ikezoe, Takeharu
AU - Hiraga, Keizo
AU - Shuto, Yusuke
AU - Yagami, Kojiro
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/11/15
Y1 - 2018/11/15
N2 - A non-volatile flip-flop (NVFF) introducing MTJ has many strong points in high endurance and read/write performance, and hence is very attractive as a component to be used for power gating of sequential circuits. However, large write-energy to MTJ becomes a big obstacle in achieving low energy dissipation. This paper proposes a NVFF circuit enabling to verify the success of a store operation to MTJ and retry it by prolonging the store time. We designed a NVFF circuit with this feature and applied it to 20,000 flip-flops in a dynamically reconfigurable processor (DRP). We conducted simulations considering write time variations caused by various factors such as process variations and thermal fluctuations. The results demonstrated that the proposed approach reduces store energy by 35-36% at four image-processing applications and the break-even time (BET) for non-volatile power gating is 2.0-2.9us at the 0.004% write error rate, at which no failures occur for the total number of NVFFs in the DRP.
AB - A non-volatile flip-flop (NVFF) introducing MTJ has many strong points in high endurance and read/write performance, and hence is very attractive as a component to be used for power gating of sequential circuits. However, large write-energy to MTJ becomes a big obstacle in achieving low energy dissipation. This paper proposes a NVFF circuit enabling to verify the success of a store operation to MTJ and retry it by prolonging the store time. We designed a NVFF circuit with this feature and applied it to 20,000 flip-flops in a dynamically reconfigurable processor (DRP). We conducted simulations considering write time variations caused by various factors such as process variations and thermal fluctuations. The results demonstrated that the proposed approach reduces store energy by 35-36% at four image-processing applications and the break-even time (BET) for non-volatile power gating is 2.0-2.9us at the 0.004% write error rate, at which no failures occur for the total number of NVFFs in the DRP.
KW - MTJ
KW - dynamically reconfigurable processor
KW - non-volatile flip-flop
KW - power gating
KW - process variation
KW - thermal fluctuation
KW - write energy
UR - http://www.scopus.com/inward/record.url?scp=85059806125&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85059806125&partnerID=8YFLogxK
U2 - 10.1109/NVMSA.2018.00023
DO - 10.1109/NVMSA.2018.00023
M3 - Conference contribution
AN - SCOPUS:85059806125
T3 - Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018
SP - 91
EP - 98
BT - Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018
Y2 - 28 August 2018 through 31 August 2018
ER -