TY - GEN
T1 - Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops
AU - Kamei, Aika
AU - Kojima, Takuya
AU - Amano, Hideharu
AU - Yokoyama, Daiki
AU - Miyauchi, Hisato
AU - Usami, Kimiyoshi
AU - Hiraga, Keizo
AU - Suzuki, Kenta
AU - Bessho, Kazuhiro
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021
Y1 - 2021
N2 - In this study, a second-generation coarse-grained reconfigurable array with non-volatile flip-flops (NVFFs), known as the non-volatile cool mega array with multi-context (NVCMA/MC), is proposed. Similar to the previous NVCMA, verify-and-retriable NVFFs (VR-NVFFs) are provided for their configuration memory, constant memory, data memory, and instruction memory. The dedicated instructions for controlling the store, verify, and restore operations of the NVFFs are provided to the microcontroller in addition to power gating functions. Based on experience of the NVCMA, four hardware contexts are introduced to maintain the configuration data for four tasks, without the sacrifice of memory leakage. The array size is expanded, and pipeline registers are introduced to reduce the trade-off between the performance and power consumption. This study mainly focuses on the energy-saving effect of the VR-NVFFs and the multi-context facility of the NVCMA/MC, including the measurement of the break-even point. The evaluation of a real chip implemented with 40 nm MTJ/MOS hybrid process technology demonstrates that the store energy is reduced by 65% with the two-step store control of the VR-NVFFs. Moreover, applications that run intermittently for intervals as short as approximately 3 μs can benefit from the multi-context power gating.
AB - In this study, a second-generation coarse-grained reconfigurable array with non-volatile flip-flops (NVFFs), known as the non-volatile cool mega array with multi-context (NVCMA/MC), is proposed. Similar to the previous NVCMA, verify-and-retriable NVFFs (VR-NVFFs) are provided for their configuration memory, constant memory, data memory, and instruction memory. The dedicated instructions for controlling the store, verify, and restore operations of the NVFFs are provided to the microcontroller in addition to power gating functions. Based on experience of the NVCMA, four hardware contexts are introduced to maintain the configuration data for four tasks, without the sacrifice of memory leakage. The array size is expanded, and pipeline registers are introduced to reduce the trade-off between the performance and power consumption. This study mainly focuses on the energy-saving effect of the VR-NVFFs and the multi-context facility of the NVCMA/MC, including the measurement of the break-even point. The evaluation of a real chip implemented with 40 nm MTJ/MOS hybrid process technology demonstrates that the store energy is reduced by 65% with the two-step store control of the VR-NVFFs. Moreover, applications that run intermittently for intervals as short as approximately 3 μs can benefit from the multi-context power gating.
KW - CGRA
KW - MTJ
KW - Non volatile flip flops
UR - http://www.scopus.com/inward/record.url?scp=85126676782&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85126676782&partnerID=8YFLogxK
U2 - 10.1109/MCSoC51149.2021.00047
DO - 10.1109/MCSoC51149.2021.00047
M3 - Conference contribution
AN - SCOPUS:85126676782
T3 - Proceedings - 2021 IEEE 14th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2021
SP - 273
EP - 280
BT - Proceedings - 2021 IEEE 14th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2021
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 14th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2021
Y2 - 20 December 2021 through 23 December 2021
ER -