@inproceedings{f13836262d71422cab7bdde08e213c6d,
title = "Evaluation of PDN impedance and power supply noise for different on-chip decoupling structures",
abstract = "Because CMOS LSIs operate at higher clock frequencies in recent years, conventional methods for obeying EMC regulations are not sufficient only at package level and board level. So chip level counter-measure is even more important to reduce EMI as an excitation source of noise. In this paper, power supply noise was evaluated by fabricating two circuit blocks in a test chip. One was with on-chip capacitance consisted of intentional MOS (metal-oxide semiconductor) capacitors and MIM (metal-insulator-metal) capacitors, and the other was without any intentional capacitors. Reduction effect of power supply noise and the impedance of PDN (power distribution network) at each circuit block were evaluated based on chip-package-board co-design. It has been found that PDN Impedance was suppressed by implementing on-chip capacitance in the high frequency region.",
keywords = "PDN impedance, measurement, on-chip capacitance, power supply noise",
author = "Haruya Fujita and Hiroki Takatani and Yosuke Tanaka and Shohei Kawaguchi and Masaomi Sato and Toshio Sudo",
year = "2013",
doi = "10.1109/EMCCompo.2013.6735189",
language = "English",
isbn = "9781479923151",
series = "EMC COMPO 2013 Proceedings - 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits",
publisher = "IEEE Computer Society",
pages = "142--146",
booktitle = "EMC COMPO 2013 Proceedings - 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits",
note = "9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, EMC COMPO 2013 ; Conference date: 15-12-2013 Through 18-12-2013",
}