GaAs high-speed data transfer network for a parallel processing system

Yoshiaki Kitaura; Atushi Kameyama; Toshiyuki Terada; Naotaka Uchitomi; Takeshi Miyagi; Toshio Sudo; Akira Maeda

GaAs high-speed data transfer network for a parallel processing system

Yoshiaki Kitaura, Atushi Kameyama, Toshiyuki Terada, Naotaka Uchitomi, Takeshi Miyagi, Toshio Sudo, Akira Maeda

Electrical Engineering and Computer Science

Research output: Contribution to conference › Paper › peer-review

Abstract

A GaAs high-speed data transfer network connecting multiple processor units (PUs) has been successfully developed in a module with 8-b slice GaAs bus logic (BL) LSIs, which fully functioned at more than 100 MHz. The GaAs multichip module consists of 12 GaAs BL LSIs in a 3 × 4 matrix. In the parallel processing system, a 4-Gb/s data transfer data (32 b × 120 MHz) can be realized by four stacked modules of 48 GaAs BLs.

Original language	English
Pages	195-198
Number of pages	4
Publication status	Published - 1990 Oct 1
Event	12th Annual IEEE Gallium Arsenide Integrated Circuit Symposium - GaAs IC - New Orleans, LA, USA Duration: 1990 Oct 7 → 1990 Oct 10

Other

Other	12th Annual IEEE Gallium Arsenide Integrated Circuit Symposium - GaAs IC
City	New Orleans, LA, USA
Period	90/10/7 → 90/10/10

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "GaAs high-speed data transfer network for a parallel processing system",

abstract = "A GaAs high-speed data transfer network connecting multiple processor units (PUs) has been successfully developed in a module with 8-b slice GaAs bus logic (BL) LSIs, which fully functioned at more than 100 MHz. The GaAs multichip module consists of 12 GaAs BL LSIs in a 3 × 4 matrix. In the parallel processing system, a 4-Gb/s data transfer data (32 b × 120 MHz) can be realized by four stacked modules of 48 GaAs BLs.",

author = "Yoshiaki Kitaura and Atushi Kameyama and Toshiyuki Terada and Naotaka Uchitomi and Takeshi Miyagi and Toshio Sudo and Akira Maeda",

year = "1990",

month = oct,

day = "1",

language = "English",

pages = "195--198",

note = "12th Annual IEEE Gallium Arsenide Integrated Circuit Symposium - GaAs IC ; Conference date: 07-10-1990 Through 10-10-1990",

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T1 - GaAs high-speed data transfer network for a parallel processing system

AU - Kitaura, Yoshiaki

AU - Kameyama, Atushi

AU - Terada, Toshiyuki

AU - Uchitomi, Naotaka

AU - Miyagi, Takeshi

AU - Sudo, Toshio

AU - Maeda, Akira

PY - 1990/10/1

Y1 - 1990/10/1

N2 - A GaAs high-speed data transfer network connecting multiple processor units (PUs) has been successfully developed in a module with 8-b slice GaAs bus logic (BL) LSIs, which fully functioned at more than 100 MHz. The GaAs multichip module consists of 12 GaAs BL LSIs in a 3 × 4 matrix. In the parallel processing system, a 4-Gb/s data transfer data (32 b × 120 MHz) can be realized by four stacked modules of 48 GaAs BLs.

AB - A GaAs high-speed data transfer network connecting multiple processor units (PUs) has been successfully developed in a module with 8-b slice GaAs bus logic (BL) LSIs, which fully functioned at more than 100 MHz. The GaAs multichip module consists of 12 GaAs BL LSIs in a 3 × 4 matrix. In the parallel processing system, a 4-Gb/s data transfer data (32 b × 120 MHz) can be realized by four stacked modules of 48 GaAs BLs.

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UR - http://www.scopus.com/inward/citedby.url?scp=0025496353&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0025496353

SP - 195

EP - 198

T2 - 12th Annual IEEE Gallium Arsenide Integrated Circuit Symposium - GaAs IC

Y2 - 7 October 1990 through 10 October 1990

ER -

GaAs high-speed data transfer network for a parallel processing system

Abstract

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ASJC Scopus subject areas

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