A hierarchical symbolic layout methodology for designing large-scale datapaths is proposed. The methodology constructs a datapath hierarchically by taking note of the bit-slice regular structure. It gives a globally optimized layout with a rapid optimizing loop. This approach has reduced design effort to 1/10 compared with conventional handcraft design (maintaining equivalent layout quality) for a datapath which includes 21K transistors. Macrocells without bit-sliced structure are also considered to be easily embedded into the final datapath layout. Moreover, as a design entry, an LT-diagram entry is allowed for a designer. The diagram is a special logic diagram which includes topological information for gates and wirings. A stick-diagram is automatically synthesized from the LT-diagram and mask layout is generated through compaction.
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|Publication status||Published - 1990 Dec 1|
|Event||Proceedings of the 12th Annual IEEE 1990 Custom Integrated Circuits Conference - CICC '90 - Boston, MA, USA|
Duration: 1990 May 13 → 1990 May 16
ASJC Scopus subject areas
- Electrical and Electronic Engineering