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Highly reliable interface of self-aligned CuSiN process with low-k SiC barrier dielectric (k=3.5) for 65nm node and beyond
T. Usami, T. Ide, Y. Kakuhara, Y. Ajima, K. Ueno, T. Maruyama, Y. Yu, E. Apen, K. Chattopadhyay, B. Van Schravendijk, N. Oda, M. Sekine
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
4
Citations
(Scopus)