@inproceedings{ac38d1eb54b34d40bf6f5cb3ae87f00b,
title = "Hybrid design of dual Vth and power gating to reduce leakage power under Vth variations",
abstract = "Increase in leakage power and Vth variation is a critical concern in leading-edge CMOS technology. Traditional dual Vth design with the worst corner model becomes difficult to achieve for low leakage because delay variation of high Vth cell is increased significantly by Vth variation. In this paper, we demonstrated that a power gated cell is more tolerant in delay variation than high Vth cell in 45nm technology. We propose hybrid design technique to use power gated cells in the dual Vth circuit to reduce standby leakage without causing performance degradation. Also, we developed an optimization methodology based on simulated annealing. The proposed technique was applied to ISCAS'85 benchmark circuits. Standby leakage power was reduced by 44% on average over the conventional dual Vth design.",
keywords = "Dual Vth, Leakage current, Low power, MTCMOS, Power gating, Vth variation",
author = "Toshiaki Shirai and Kimiyoshi Usami",
year = "2008",
month = dec,
day = "1",
doi = "10.1109/SOCDC.2008.4815634",
language = "English",
isbn = "9781424425990",
series = "2008 International SoC Design Conference, ISOCC 2008",
pages = "I310--I313",
booktitle = "2008 International SoC Design Conference, ISOCC 2008",
note = "2008 International SoC Design Conference, ISOCC 2008 ; Conference date: 24-11-2008 Through 25-11-2008",
}