Low-impedance power distribution network of decoupling capacitor embedded interposers for 3-D integrated LSI system

Katsuya Kikuchi; Koichi Takemura; Chihiro Ueda; Osamu Shimada; Toshio Gomyo; Yukiharu Takeuchi; Toshikazu Okubo; Kazuhiro Baba; Masahiro Aoyagi; Toshio Sudo; Kanji Otsuka

doi:10.1109/EPEPS.2009.5338487

Low-impedance power distribution network of decoupling capacitor embedded interposers for 3-D integrated LSI system

Katsuya Kikuchi, Koichi Takemura, Chihiro Ueda, Osamu Shimada, Toshio Gomyo, Yukiharu Takeuchi, Toshikazu Okubo, Kazuhiro Baba, Masahiro Aoyagi, Toshio Sudo, Kanji Otsuka

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

We evaluated low-impedance power distribution network (PDN) of decoupling capacitor embedded interposers for 3-D integrated LSI system. Measurements are carried out using the developed impedance analyzer system of a wide frequency range for evaluating ultralow impedance, and calculations are carried out using 2.5-D finite element method (FEM) electromagnetic field simulator. We fabricated various types of capacitor mounted or capacitor embedded interposers test element group (TEG), such as surface-mounted and embedded chip capacitors, and thin film capacitors on silicon interposers using the same simple design to compare measurement results with calculation ones. As a result, the chip capacitor embedded organic interposer TEG and thin film capacitor embedded silicon interposer TEG could provide low PDN impedance at a wide frequency range of up to 10 GHz. In particular, the interposer TEGs of the thin film capacitor embedded interposer that shows a low impedance of approximately 0.001 ? could be evaluated and calculated accurately. By using chip capacitor embedded or thin film capacitor embedded interposers for 3-D integrated LSI system, it is expected that the PDN of the system can be achieved ultralow PDN impedance.

Original language	English
Title of host publication	2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09
Pages	25-28
Number of pages	4
DOIs	https://doi.org/10.1109/EPEPS.2009.5338487
Publication status	Published - 2009
Externally published	Yes
Event	2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09 - Portland, OR, United States Duration: 2009 Oct 19 → 2009 Oct 21

Publication series

Name	2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09

Conference

Conference	2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09
Country/Territory	United States
City	Portland, OR
Period	09/10/19 → 09/10/21

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/EPEPS.2009.5338487

Cite this

Kikuchi, K., Takemura, K., Ueda, C., Shimada, O., Gomyo, T., Takeuchi, Y., Okubo, T., Baba, K., Aoyagi, M., Sudo, T., & Otsuka, K. (2009). Low-impedance power distribution network of decoupling capacitor embedded interposers for 3-D integrated LSI system. In 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09 (pp. 25-28). [5338487] (2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09). https://doi.org/10.1109/EPEPS.2009.5338487

Low-impedance power distribution network of decoupling capacitor embedded interposers for 3-D integrated LSI system. / Kikuchi, Katsuya; Takemura, Koichi; Ueda, Chihiro et al.

2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09. 2009. p. 25-28 5338487 (2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kikuchi, K, Takemura, K, Ueda, C, Shimada, O, Gomyo, T, Takeuchi, Y, Okubo, T, Baba, K, Aoyagi, M, Sudo, T & Otsuka, K 2009, Low-impedance power distribution network of decoupling capacitor embedded interposers for 3-D integrated LSI system. in 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09., 5338487, 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09, pp. 25-28, 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09, Portland, OR, United States, 09/10/19. https://doi.org/10.1109/EPEPS.2009.5338487

Kikuchi K, Takemura K, Ueda C, Shimada O, Gomyo T, Takeuchi Y et al. Low-impedance power distribution network of decoupling capacitor embedded interposers for 3-D integrated LSI system. In 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09. 2009. p. 25-28. 5338487. (2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09). doi: 10.1109/EPEPS.2009.5338487

Kikuchi, Katsuya ; Takemura, Koichi ; Ueda, Chihiro et al. / Low-impedance power distribution network of decoupling capacitor embedded interposers for 3-D integrated LSI system. 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09. 2009. pp. 25-28 (2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09).

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abstract = "We evaluated low-impedance power distribution network (PDN) of decoupling capacitor embedded interposers for 3-D integrated LSI system. Measurements are carried out using the developed impedance analyzer system of a wide frequency range for evaluating ultralow impedance, and calculations are carried out using 2.5-D finite element method (FEM) electromagnetic field simulator. We fabricated various types of capacitor mounted or capacitor embedded interposers test element group (TEG), such as surface-mounted and embedded chip capacitors, and thin film capacitors on silicon interposers using the same simple design to compare measurement results with calculation ones. As a result, the chip capacitor embedded organic interposer TEG and thin film capacitor embedded silicon interposer TEG could provide low PDN impedance at a wide frequency range of up to 10 GHz. In particular, the interposer TEGs of the thin film capacitor embedded interposer that shows a low impedance of approximately 0.001 ? could be evaluated and calculated accurately. By using chip capacitor embedded or thin film capacitor embedded interposers for 3-D integrated LSI system, it is expected that the PDN of the system can be achieved ultralow PDN impedance.",

author = "Katsuya Kikuchi and Koichi Takemura and Chihiro Ueda and Osamu Shimada and Toshio Gomyo and Yukiharu Takeuchi and Toshikazu Okubo and Kazuhiro Baba and Masahiro Aoyagi and Toshio Sudo and Kanji Otsuka",

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AU - Gomyo, Toshio

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Low-impedance power distribution network of decoupling capacitor embedded interposers for 3-D integrated LSI system

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