Low-power-consumption 10-Gbps GaAs 8:1 multiplexer/1:8 demultiplexer

Nobuhide Yoshida, Masahiro Fujii, Takao Atsumo, Keiichi Numata, Shuji Asai, Michihisa Kohno, Hirokazu Oikawa, Hiroaki Tsutsui, Tadeshi Maeda

Research output: Contribution to conferencePaperpeer-review

8 Citations (Scopus)


An ECL-compatible 10-Gbps GaAs 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) has been developed. To decrease power consumption and to maximize phase margin, the clock-generating circuit employs source-coupled FET logic (SCFL) circuits. Also, cascade-connected source-follower circuits are used in the clock buffer. These circuits can reduce the power consumption when the fan-out number is large. Direct coupled FET logic (DCFL) circuits are employed for the 2:1 MUX/1:2 DEMUX circuits operating below 5 Gbps. The ICs, which are mounted on ceramic packages, operate at up to 10 Gbps with a power consumption of 1.2 W for the MUX and 1.0 W for the DEMUX at ECL-compatible supply voltages. These power-consumption values are one-third of the previously reported values.

Original languageEnglish
Number of pages4
Publication statusPublished - 1997
Externally publishedYes
EventProceedings of the 1997 19th Annual GaAs IC Symposium - Anaheim, CA, USA
Duration: 1997 Oct 121997 Oct 15


OtherProceedings of the 1997 19th Annual GaAs IC Symposium
CityAnaheim, CA, USA

ASJC Scopus subject areas

  • General Engineering


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