Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz

Tadashi Maeda; Hitoshi Yano; Shinichi Hori; Noriaki Matsuno; Tomoyuki Yamase; Takashi Tokairin; Robert Walkington; Nobuhide Yoshida; Keiichi Numata; Kiyoshi Yanagisawa; Yuji Takahashi; Masahiro Fujii; Hikaru Hida

doi:10.1109/JSSC.2005.862339

Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz

Tadashi Maeda, Hitoshi Yano, Shinichi Hori, Noriaki Matsuno, Tomoyuki Yamase, Takashi Tokairin, Robert Walkington, Nobuhide Yoshida, Keiichi Numata, Kiyoshi Yanagisawa, Yuji Takahashi, Masahiro Fujii, Hikaru Hida

Research output: Contribution to journal › Article › peer-review

43 Citations (Scopus)

Abstract

This paper describes a low-power-consumption direct-conversion CMOS transceiver for WLAN systems operating at 4.9-5.95 GHz. Its power consumption is reduced by using a resonator-switching wide-dynamic-range LNA. The broad tuning range needed for multiple-channel-bandwidth systems is provided by a single widely tunable low-pass filter based on negative-source-degeneration-resistor transconductors, and its automatic frequency-band-selection PLL supports multiple standard 5-GHz WLAN systems. The system noise figure is 4.4 dB at a maximum gain of 74 dB, and the receiver IIP3 is +5 dBm and -21 dBm for the minimum and maximum gain modes, respectively. The error vector magnitude (EVM) of the transmitted signal is 2.6%. The current consumption is extremely low, 65 mA in the transmitter path and 60 mA in the receiver path.

Original language	English
Pages (from-to)	375-382
Number of pages	8
Journal	IEEE Journal of Solid-State Circuits
Volume	41
Issue number	2
DOIs	https://doi.org/10.1109/JSSC.2005.862339
Publication status	Published - 2006 Feb
Externally published	Yes

Keywords

CMOS transceiver
Frequency synthesizer
HiSWANa
HiperLAN/2
IEEE 802.11a
Low-noise amplifier (LNA)
Low-pass filter (LFF)
Orthogonal frequency division multiplexing (OFDM)
Wireless LAN (WLAN)

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/JSSC.2005.862339

Cite this

Maeda, T., Yano, H., Hori, S., Matsuno, N., Yamase, T., Tokairin, T., Walkington, R., Yoshida, N., Numata, K., Yanagisawa, K., Takahashi, Y., Fujii, M., & Hida, H. (2006). Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz. IEEE Journal of Solid-State Circuits, 41(2), 375-382. https://doi.org/10.1109/JSSC.2005.862339

Maeda, T, Yano, H, Hori, S, Matsuno, N, Yamase, T, Tokairin, T, Walkington, R, Yoshida, N, Numata, K, Yanagisawa, K, Takahashi, Y, Fujii, M & Hida, H 2006, 'Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz', IEEE Journal of Solid-State Circuits, vol. 41, no. 2, pp. 375-382. https://doi.org/10.1109/JSSC.2005.862339

@article{8d250e9977b8474e88b8803a0a0c7fed,

title = "Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz",

abstract = "This paper describes a low-power-consumption direct-conversion CMOS transceiver for WLAN systems operating at 4.9-5.95 GHz. Its power consumption is reduced by using a resonator-switching wide-dynamic-range LNA. The broad tuning range needed for multiple-channel-bandwidth systems is provided by a single widely tunable low-pass filter based on negative-source-degeneration-resistor transconductors, and its automatic frequency-band-selection PLL supports multiple standard 5-GHz WLAN systems. The system noise figure is 4.4 dB at a maximum gain of 74 dB, and the receiver IIP3 is +5 dBm and -21 dBm for the minimum and maximum gain modes, respectively. The error vector magnitude (EVM) of the transmitted signal is 2.6%. The current consumption is extremely low, 65 mA in the transmitter path and 60 mA in the receiver path.",

keywords = "CMOS transceiver, Frequency synthesizer, HiSWANa, HiperLAN/2, IEEE 802.11a, Low-noise amplifier (LNA), Low-pass filter (LFF), Orthogonal frequency division multiplexing (OFDM), Wireless LAN (WLAN)",

author = "Tadashi Maeda and Hitoshi Yano and Shinichi Hori and Noriaki Matsuno and Tomoyuki Yamase and Takashi Tokairin and Robert Walkington and Nobuhide Yoshida and Keiichi Numata and Kiyoshi Yanagisawa and Yuji Takahashi and Masahiro Fujii and Hikaru Hida",

year = "2006",

month = feb,

doi = "10.1109/JSSC.2005.862339",

language = "English",

volume = "41",

pages = "375--382",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "2",

}

TY - JOUR

T1 - Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz

AU - Maeda, Tadashi

AU - Yano, Hitoshi

AU - Hori, Shinichi

AU - Matsuno, Noriaki

AU - Yamase, Tomoyuki

AU - Tokairin, Takashi

AU - Walkington, Robert

AU - Yoshida, Nobuhide

AU - Numata, Keiichi

AU - Yanagisawa, Kiyoshi

AU - Takahashi, Yuji

AU - Fujii, Masahiro

AU - Hida, Hikaru

PY - 2006/2

Y1 - 2006/2

N2 - This paper describes a low-power-consumption direct-conversion CMOS transceiver for WLAN systems operating at 4.9-5.95 GHz. Its power consumption is reduced by using a resonator-switching wide-dynamic-range LNA. The broad tuning range needed for multiple-channel-bandwidth systems is provided by a single widely tunable low-pass filter based on negative-source-degeneration-resistor transconductors, and its automatic frequency-band-selection PLL supports multiple standard 5-GHz WLAN systems. The system noise figure is 4.4 dB at a maximum gain of 74 dB, and the receiver IIP3 is +5 dBm and -21 dBm for the minimum and maximum gain modes, respectively. The error vector magnitude (EVM) of the transmitted signal is 2.6%. The current consumption is extremely low, 65 mA in the transmitter path and 60 mA in the receiver path.

AB - This paper describes a low-power-consumption direct-conversion CMOS transceiver for WLAN systems operating at 4.9-5.95 GHz. Its power consumption is reduced by using a resonator-switching wide-dynamic-range LNA. The broad tuning range needed for multiple-channel-bandwidth systems is provided by a single widely tunable low-pass filter based on negative-source-degeneration-resistor transconductors, and its automatic frequency-band-selection PLL supports multiple standard 5-GHz WLAN systems. The system noise figure is 4.4 dB at a maximum gain of 74 dB, and the receiver IIP3 is +5 dBm and -21 dBm for the minimum and maximum gain modes, respectively. The error vector magnitude (EVM) of the transmitted signal is 2.6%. The current consumption is extremely low, 65 mA in the transmitter path and 60 mA in the receiver path.

KW - CMOS transceiver

KW - Frequency synthesizer

KW - HiSWANa

KW - HiperLAN/2

KW - IEEE 802.11a

KW - Low-noise amplifier (LNA)

KW - Low-pass filter (LFF)

KW - Orthogonal frequency division multiplexing (OFDM)

KW - Wireless LAN (WLAN)

UR - http://www.scopus.com/inward/record.url?scp=31644444944&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=31644444944&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2005.862339

DO - 10.1109/JSSC.2005.862339

M3 - Article

AN - SCOPUS:31644444944

SN - 0018-9200

VL - 41

SP - 375

EP - 382

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 2

ER -

Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz

Abstract

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this