Low-power design technique for ASICs by partially reducing supply voltage

Kimiyoshi Usami; Takashi Ishikawa; Masahiro Kanazawa; Hiroko Kotani

Low-power design technique for ASICs by partially reducing supply voltage

Kimiyoshi Usami, Takashi Ishikawa, Masahiro Kanazawa, Hiroko Kotani

Research output: Contribution to journal › Conference article › peer-review

Abstract

In this paper, we discuss power reduction by comparing two different design techniques targeting low-power ASICs: clustered voltage scaling (CVS) and gate resizing. The CVS is a technique to reduce supply voltage partially, allowing to reduce power without performance degradation. As a result of applying to real gate-array circuits, the CVS reduced power by 30-60% even at dominant wire capacitance, while the gate re-sizing got less effective. The CVS is considered to be a key technique toward deep sub-micron age, in which the wire capacitance will be further dominant.

Original language	English
Pages (from-to)	301-304
Number of pages	4
Journal	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
Publication status	Published - 1996 Jan 1
Externally published	Yes
Event	Proceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit - Rochester, NY, USA Duration: 1996 Sept 23 → 1996 Sept 27

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "Low-power design technique for ASICs by partially reducing supply voltage",

abstract = "In this paper, we discuss power reduction by comparing two different design techniques targeting low-power ASICs: clustered voltage scaling (CVS) and gate resizing. The CVS is a technique to reduce supply voltage partially, allowing to reduce power without performance degradation. As a result of applying to real gate-array circuits, the CVS reduced power by 30-60% even at dominant wire capacitance, while the gate re-sizing got less effective. The CVS is considered to be a key technique toward deep sub-micron age, in which the wire capacitance will be further dominant.",

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AU - Usami, Kimiyoshi

AU - Ishikawa, Takashi

AU - Kanazawa, Masahiro

AU - Kotani, Hiroko

PY - 1996/1/1

Y1 - 1996/1/1

N2 - In this paper, we discuss power reduction by comparing two different design techniques targeting low-power ASICs: clustered voltage scaling (CVS) and gate resizing. The CVS is a technique to reduce supply voltage partially, allowing to reduce power without performance degradation. As a result of applying to real gate-array circuits, the CVS reduced power by 30-60% even at dominant wire capacitance, while the gate re-sizing got less effective. The CVS is considered to be a key technique toward deep sub-micron age, in which the wire capacitance will be further dominant.

AB - In this paper, we discuss power reduction by comparing two different design techniques targeting low-power ASICs: clustered voltage scaling (CVS) and gate resizing. The CVS is a technique to reduce supply voltage partially, allowing to reduce power without performance degradation. As a result of applying to real gate-array circuits, the CVS reduced power by 30-60% even at dominant wire capacitance, while the gate re-sizing got less effective. The CVS is considered to be a key technique toward deep sub-micron age, in which the wire capacitance will be further dominant.

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M3 - Conference article

AN - SCOPUS:0029726316

SN - 1063-0988

SP - 301

EP - 304

JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

T2 - Proceedings of the 1996 9th Annual IEEE International ASIC Conference and Exhibit

Y2 - 23 September 1996 through 27 September 1996

ER -

Low-power design technique for ASICs by partially reducing supply voltage

Abstract

ASJC Scopus subject areas

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