Material and process challenges for interconnects in nanoelectronics era

Kazuyoshi Ueno

doi:10.1109/VTSA.2010.5488945

Material and process challenges for interconnects in nanoelectronics era

Kazuyoshi Ueno

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

Cu/low-k interconnects have been used in LSI fabrication. However, several difficult challenges need to be overcome for 22-nm node devices and beyond. These challenges include an increase in resistivity, degradation of the electromigration reliability, and the low mechanical strength of low-k dielectrics. To overcome these problems, it is essential to not only improve Cu/low-k fabrication processes but also to develop alternative approaches based on emerging technologies such as 3D interconnects, nanocarbon interconnects, and optical interconnects. This paper reviews the problems and potential solutions, and describes approaches such as supercritical (SC) annealing for grain growth enhancement, CoWP caps for electromigration (EM) reliability improvement, and electroless barrier deposition for ultrathin barrier layer.

Original language	English
Title of host publication	Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010
Pages	64-65
Number of pages	2
DOIs	https://doi.org/10.1109/VTSA.2010.5488945
Publication status	Published - 2010 Oct 20
Event	2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010 - Hsin Chu, Taiwan, Province of China Duration: 2010 Apr 26 → 2010 Apr 28

Publication series

Name	Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010

Conference

Conference	2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010
Country/Territory	Taiwan, Province of China
City	Hsin Chu
Period	10/4/26 → 10/4/28

ASJC Scopus subject areas

Computer Networks and Communications
Hardware and Architecture

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10.1109/VTSA.2010.5488945

Cite this

Ueno, K. (2010). Material and process challenges for interconnects in nanoelectronics era. In Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010 (pp. 64-65). Article 5488945 (Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010). https://doi.org/10.1109/VTSA.2010.5488945

Material and process challenges for interconnects in nanoelectronics era. / Ueno, Kazuyoshi.
Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010. 2010. p. 64-65 5488945 (Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ueno, K 2010, Material and process challenges for interconnects in nanoelectronics era. in Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010., 5488945, Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010, pp. 64-65, 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010, Hsin Chu, Taiwan, Province of China, 10/4/26. https://doi.org/10.1109/VTSA.2010.5488945

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Material and process challenges for interconnects in nanoelectronics era

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