TY - GEN
T1 - Measurement and analysis of anti-resonance peak in total PDN impedance
AU - Kiyoshige, Sho
AU - Ichimura, Wataru
AU - Terasaki, Masahiro
AU - Kobayashi, Ryota
AU - Kubo, Genki
AU - Otsuka, Hiroki
AU - Sudo, Toshio
PY - 2013/12/24
Y1 - 2013/12/24
N2 - Power integrity is a serious issue in the modern CMOS digital systems, because power supply noise excited in core circuits induces logic instability and electromagnetic radiation. Therefore, chip-package co-design is becoming important by taking into consideration the total impedance of power distribution network (PDN) seen from the chip. Especially, parallel resonance peaks in the PDN due to the chip-package interaction induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by adding different RC circuit to the intrinsic on-die RC circuit of chip. Three test chips were assumed to be designed with different on-chip PDN properties. The measurement and analysis of power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip.
AB - Power integrity is a serious issue in the modern CMOS digital systems, because power supply noise excited in core circuits induces logic instability and electromagnetic radiation. Therefore, chip-package co-design is becoming important by taking into consideration the total impedance of power distribution network (PDN) seen from the chip. Especially, parallel resonance peaks in the PDN due to the chip-package interaction induces the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by adding different RC circuit to the intrinsic on-die RC circuit of chip. Three test chips were assumed to be designed with different on-chip PDN properties. The measurement and analysis of power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip.
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M3 - Conference contribution
AN - SCOPUS:84890742491
SN - 9781467349796
T3 - IEEE International Symposium on Electromagnetic Compatibility
SP - 931
EP - 936
BT - Proceedings of the 2013 International Symposium on Electromagnetic Compatibility, EMC Europe 2013
T2 - 2013 International Symposium on Electromagnetic Compatibility, EMC Europe 2013
Y2 - 2 September 2013 through 6 September 2013
ER -