TY - GEN
T1 - Measurement of SSO noise and PDN impedance of 3D SiP with 4k-IO widebus structure
AU - Tanaka, Yosuke
AU - Takatani, Hiroki
AU - Fujita, Haruya
AU - Oizono, Yoshiaki
AU - Nabeshima, Yoshitaka
AU - Sudo, Toshio
AU - Sakai, Atsushi
AU - Uchiyama, Shiro
AU - Ikeda, Hiroaki
PY - 2012/12/1
Y1 - 2012/12/1
N2 - Simultaneous switching output buffer (SSO) noise and impedance of power distribution network (PDN) for a 3D systemin package (SiP) with 4k-IO widebus structure has been investigated. The 3D SiP consisted of 3 stacked chips and an organic interposer. These three chips were a memory chip on the top, a silicon interposer in the middle, and a logic chip on the bottom. The size of each chip was the same, and 9.93 mm by 9.93 mm. More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer. Next, these 3 stacked chips were assembled on the organic interposer, whose size was 26 mm by 26mm. SSO noise is one of critical issues for the 3D SiP with 4k-IO widebus structure. So, the SSO noise was measured in the miniIO power supply system in an evaluation board. Furthermore the PDN impedance for each chip was measured by direct contact method. Then, the total PDN impedance was synthesized to confirm the anti-resonance peak of it.
AB - Simultaneous switching output buffer (SSO) noise and impedance of power distribution network (PDN) for a 3D systemin package (SiP) with 4k-IO widebus structure has been investigated. The 3D SiP consisted of 3 stacked chips and an organic interposer. These three chips were a memory chip on the top, a silicon interposer in the middle, and a logic chip on the bottom. The size of each chip was the same, and 9.93 mm by 9.93 mm. More than 4096 of through silicon vias (TSV's) were formed to the silicon interposer. Next, these 3 stacked chips were assembled on the organic interposer, whose size was 26 mm by 26mm. SSO noise is one of critical issues for the 3D SiP with 4k-IO widebus structure. So, the SSO noise was measured in the miniIO power supply system in an evaluation board. Furthermore the PDN impedance for each chip was measured by direct contact method. Then, the total PDN impedance was synthesized to confirm the anti-resonance peak of it.
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U2 - 10.1109/EPEPS.2012.6457850
DO - 10.1109/EPEPS.2012.6457850
M3 - Conference contribution
AN - SCOPUS:84874470033
SN - 9781467325394
T3 - 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012
SP - 91
EP - 94
BT - 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012
T2 - 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2012
Y2 - 21 October 2012 through 24 October 2012
ER -