Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization

Kimiyoshi Usami; Sosuke Akiba; Hideharu Amano; Takeharu Ikezoe; Keizo Hiraga; Kenta Suzuki; Yasuo Kanda

doi:10.1109/COOLCHIPS49199.2020.9097630

Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization

Kimiyoshi Usami, Sosuke Akiba, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Kenta Suzuki, Yasuo Kanda

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

Non-volatile power gating introducing MTJ into a flip-flop is an attractive technique for IoT devices. However, the time required for a successful store operation to MTJs varies at non-volatile flip-flops (NVFFs) due to process and voltage variation. This paper describes implementation and real-chip evaluation of a non-volatile Coarse Grained Reconfigurable Array employing verify-and-retryable NVFF (VR-NVFF) circuits and two-step store (TSS) control by instructions of a microcontroller. Test chips fabricated in a 40nm CMOS/MTJ hybrid technology have demonstrated that the TSS approach using both 30ns/100ns store operations reduces power by 37-42% when running an image processing program at 100MHz.

Original language	English
Title of host publication	IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728163475
DOIs	https://doi.org/10.1109/COOLCHIPS49199.2020.9097630
Publication status	Published - 2020 Apr
Event	23rd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Kokubunji, Japan Duration: 2020 Apr 15 → 2020 Apr 17

Publication series

Name	IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings

Conference

Conference	23rd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020
Country/Territory	Japan
City	Kokubunji
Period	20/4/15 → 20/4/17

Keywords

Coarse Grained Reconfigurable Array
MTJ
Non-volatile
energy
flip-flop
power gating

ASJC Scopus subject areas

Computer Graphics and Computer-Aided Design
Hardware and Architecture
Software
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

Access to Document

10.1109/COOLCHIPS49199.2020.9097630

Cite this

Usami, K., Akiba, S., Amano, H., Ikezoe, T., Hiraga, K., Suzuki, K., & Kanda, Y. (2020). Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization. In IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings [9097630] (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/COOLCHIPS49199.2020.9097630

Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization. / Usami, Kimiyoshi; Akiba, Sosuke; Amano, Hideharu et al.
IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. 9097630 (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Usami, K, Akiba, S, Amano, H, Ikezoe, T, Hiraga, K, Suzuki, K & Kanda, Y 2020, Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization. in IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings., 9097630, IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 23rd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020, Kokubunji, Japan, 20/4/15. https://doi.org/10.1109/COOLCHIPS49199.2020.9097630

Usami K, Akiba S, Amano H, Ikezoe T, Hiraga K, Suzuki K et al. Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization. In IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2020. 9097630. (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings). doi: 10.1109/COOLCHIPS49199.2020.9097630

Usami, Kimiyoshi ; Akiba, Sosuke ; Amano, Hideharu et al. / Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization. IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings).

@inproceedings{b76e07dd105a440789aa8dd94f9cefd6,

title = "Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization",

abstract = "Non-volatile power gating introducing MTJ into a flip-flop is an attractive technique for IoT devices. However, the time required for a successful store operation to MTJs varies at non-volatile flip-flops (NVFFs) due to process and voltage variation. This paper describes implementation and real-chip evaluation of a non-volatile Coarse Grained Reconfigurable Array employing verify-and-retryable NVFF (VR-NVFF) circuits and two-step store (TSS) control by instructions of a microcontroller. Test chips fabricated in a 40nm CMOS/MTJ hybrid technology have demonstrated that the TSS approach using both 30ns/100ns store operations reduces power by 37-42% when running an image processing program at 100MHz.",

keywords = "Coarse Grained Reconfigurable Array, MTJ, Non-volatile, energy, flip-flop, power gating",

author = "Kimiyoshi Usami and Sosuke Akiba and Hideharu Amano and Takeharu Ikezoe and Keizo Hiraga and Kenta Suzuki and Yasuo Kanda",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 23rd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 ; Conference date: 15-04-2020 Through 17-04-2020",

year = "2020",

month = apr,

doi = "10.1109/COOLCHIPS49199.2020.9097630",

language = "English",

series = "IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings",

}

TY - GEN

T1 - Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization

AU - Usami, Kimiyoshi

AU - Akiba, Sosuke

AU - Amano, Hideharu

AU - Ikezoe, Takeharu

AU - Hiraga, Keizo

AU - Suzuki, Kenta

AU - Kanda, Yasuo

PY - 2020/4

Y1 - 2020/4

N2 - Non-volatile power gating introducing MTJ into a flip-flop is an attractive technique for IoT devices. However, the time required for a successful store operation to MTJs varies at non-volatile flip-flops (NVFFs) due to process and voltage variation. This paper describes implementation and real-chip evaluation of a non-volatile Coarse Grained Reconfigurable Array employing verify-and-retryable NVFF (VR-NVFF) circuits and two-step store (TSS) control by instructions of a microcontroller. Test chips fabricated in a 40nm CMOS/MTJ hybrid technology have demonstrated that the TSS approach using both 30ns/100ns store operations reduces power by 37-42% when running an image processing program at 100MHz.

AB - Non-volatile power gating introducing MTJ into a flip-flop is an attractive technique for IoT devices. However, the time required for a successful store operation to MTJs varies at non-volatile flip-flops (NVFFs) due to process and voltage variation. This paper describes implementation and real-chip evaluation of a non-volatile Coarse Grained Reconfigurable Array employing verify-and-retryable NVFF (VR-NVFF) circuits and two-step store (TSS) control by instructions of a microcontroller. Test chips fabricated in a 40nm CMOS/MTJ hybrid technology have demonstrated that the TSS approach using both 30ns/100ns store operations reduces power by 37-42% when running an image processing program at 100MHz.

KW - Coarse Grained Reconfigurable Array

KW - MTJ

KW - Non-volatile

KW - energy

KW - flip-flop

KW - power gating

UR - http://www.scopus.com/inward/record.url?scp=85086041245&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85086041245&partnerID=8YFLogxK

U2 - 10.1109/COOLCHIPS49199.2020.9097630

DO - 10.1109/COOLCHIPS49199.2020.9097630

M3 - Conference contribution

AN - SCOPUS:85086041245

T3 - IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings

BT - IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 23rd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020

Y2 - 15 April 2020 through 17 April 2020

ER -

Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this