Novel Viterbi Decoder VLSI Implementation and its Performance

Shuji Kubota, Shuzo Kato, Tsunehachi Ishitani

Research output: Contribution to journalArticlepeer-review

35 Citations (Scopus)


This paper presents an advanced, high-speed, and universal-coding-rate Viterbi decoder VLSI implementation. Two novel circuit design schemes have been proposed: “scarce state transition (SST)” and “direct high-coding-rate convolutional code generation and variable-rate Viterbi decoding.” SST makes it possible to omit the final decision circuit and to reduce the required path memory length without degrading Pe performance. Moreover, the power consumption of the SST Viterbi decoder is significantly reduced when implemented as a CMOS devices. These features overcome the speed limits of high-speed and high-coding-gain Viterbi decoder VLSI’s in the rate one-half mode imposed by the thermal limitation. Moreover, the proposed direct high-coding-rate convolutional code generation and variable-rate Viterbi decoding scheme make it possible to realize a simple and variable coding-rate forward-error-correction circuit by changing only the branch metric calculation ROM tables. By employing these schemes, high-speed (25 Mb/s) and universal-coding-rate Viterbi decoder VLSI’s have been developed. Experimental results employing developed Viterbi decoder VLSI’s confirm satisfactoryPe performance and high operation speeds under various conditions, for example, AWGN, cochannel interference, and adjacent channel interference environments.

Original languageEnglish
Pages (from-to)1170-1178
Number of pages9
JournalIEEE Transactions on Communications
Issue number8
Publication statusPublished - 1993 Aug
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


Dive into the research topics of 'Novel Viterbi Decoder VLSI Implementation and its Performance'. Together they form a unique fingerprint.

Cite this