Numerical Analysis of GaAs MESFETs with p-Buffer Layer on Semi-Insulating Substrate Including Deep TRAPS

K. Horio; H. Yanai

doi:10.1049/el:19890064

Numerical Analysis of GaAs MESFETs with p-Buffer Layer on Semi-Insulating Substrate Including Deep TRAPS

K. Horio, H. Yanai

Research output: Contribution to journal › Article › peer-review

Abstract

Numerical analysis of GaAs MESFETs with a p-buffer layer on the semi-insulating substrate is presented in which impurity compensation by traps is included. Using a p-buffer layer is shown to be effective in minimising the short-channel effects as in the case of using a substrate with high density of traps.

Original language	English
Pages (from-to)	86-88
Number of pages	3
Journal	Electronics Letters
Volume	25
Issue number	2
DOIs	https://doi.org/10.1049/el:19890064
Publication status	Published - 1989 Sept 1

Keywords

FETs
Integrated circuits
Semiconductor devices and materials

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1049/el:19890064

Cite this

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title = "Numerical Analysis of GaAs MESFETs with p-Buffer Layer on Semi-Insulating Substrate Including Deep TRAPS",

abstract = "Numerical analysis of GaAs MESFETs with a p-buffer layer on the semi-insulating substrate is presented in which impurity compensation by traps is included. Using a p-buffer layer is shown to be effective in minimising the short-channel effects as in the case of using a substrate with high density of traps.",

keywords = "FETs, Integrated circuits, Semiconductor devices and materials",

author = "K. Horio and H. Yanai",

year = "1989",

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doi = "10.1049/el:19890064",

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AU - Horio, K.

AU - Yanai, H.

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Y1 - 1989/9/1

N2 - Numerical analysis of GaAs MESFETs with a p-buffer layer on the semi-insulating substrate is presented in which impurity compensation by traps is included. Using a p-buffer layer is shown to be effective in minimising the short-channel effects as in the case of using a substrate with high density of traps.

AB - Numerical analysis of GaAs MESFETs with a p-buffer layer on the semi-insulating substrate is presented in which impurity compensation by traps is included. Using a p-buffer layer is shown to be effective in minimising the short-channel effects as in the case of using a substrate with high density of traps.

KW - FETs

KW - Integrated circuits

KW - Semiconductor devices and materials

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U2 - 10.1049/el:19890064

DO - 10.1049/el:19890064

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JF - Electronics Letters

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ER -

Numerical Analysis of GaAs MESFETs with p-Buffer Layer on Semi-Insulating Substrate Including Deep TRAPS

Abstract

Keywords

ASJC Scopus subject areas

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