TY - GEN
T1 - Numerical simulation of GaAs MESFET's with heavily compensated substrates.
AU - Horio, K.
AU - Yanai, H.
AU - Ikoma, T.
PY - 1987
Y1 - 1987
N2 - The authors describe numerical simulations of GaAs MESFETs (metal-semiconductor field-effect transistors) on a semi-insulating substrate in which impurities are compensated by deep traps. It is shown that higher acceptor density in the substrate results in lower device current due to the formation of a space-charge layer at the channel-substrate interface. It is also shown that drain currents increase continuously because electrons are injected to fill the traps in the substrate and a current path through the substrate is formed. This substrate current becomes pronounced for shorter-gate-length MESFETs on a substrate with lower impurity densities. It is suggested that to minimize short-channel effects in GaAs MESFETs, impurity densities in the semi-insulating substrate must be high.
AB - The authors describe numerical simulations of GaAs MESFETs (metal-semiconductor field-effect transistors) on a semi-insulating substrate in which impurities are compensated by deep traps. It is shown that higher acceptor density in the substrate results in lower device current due to the formation of a space-charge layer at the channel-substrate interface. It is also shown that drain currents increase continuously because electrons are injected to fill the traps in the substrate and a current path through the substrate is formed. This substrate current becomes pronounced for shorter-gate-length MESFETs on a substrate with lower impurity densities. It is suggested that to minimize short-channel effects in GaAs MESFETs, impurity densities in the semi-insulating substrate must be high.
UR - http://www.scopus.com/inward/record.url?scp=0023526698&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0023526698&partnerID=8YFLogxK
U2 - 10.1109/nascod.1987.721186
DO - 10.1109/nascod.1987.721186
M3 - Conference contribution
AN - SCOPUS:0023526698
SN - 0906783720
SN - 9780906783726
T3 - NASECODE V Proc Fifth Int Conf Numer Anal Semicond Devices Integr Circuit
SP - 237
EP - 242
BT - NASECODE V Proc Fifth Int Conf Numer Anal Semicond Devices Integr Circuit
PB - Publ by IEEE
T2 - NASECODE V: Proceedings of the Fifth International Conference on the Numerical Analysis of Semiconductor Devices and Integrated Circuits
Y2 - 17 June 1987 through 19 June 1987
ER -