TY - GEN
T1 - On-chip power integrity evaluation system
AU - Nabeshima, Yoshitaka
AU - Oizono, Yoshiaki
AU - Okumura, Takafumi
AU - Sudo, Toshio
PY - 2011/12/1
Y1 - 2011/12/1
N2 - Power supply disturbance excited by simultaneous switching output (SSO) circuits or core circuits is a serious issue in a system-in-package (SIP), especially in 3D stacked die package, because much more I/O circuits and core circuits excited simultaneously in synchronized with clock edges than the case of single die package. Therefore, decoupling schemes in such SiP's must be carefully designed including on-chip capacitance as well as off-chip capacitance so as to reduce the impedance of power distribution network (PDN) as low as possible up to high frequency range. In this paper, an on-chip power integrity evaluation system has been established using a test chip with both noise generating circuits and monitoring circuits for on-chip power supply noise. On-chip power integrity has been examined and compared for the cases with and without on-chip capacitance and for the various embedded capacitors inside an interposer.
AB - Power supply disturbance excited by simultaneous switching output (SSO) circuits or core circuits is a serious issue in a system-in-package (SIP), especially in 3D stacked die package, because much more I/O circuits and core circuits excited simultaneously in synchronized with clock edges than the case of single die package. Therefore, decoupling schemes in such SiP's must be carefully designed including on-chip capacitance as well as off-chip capacitance so as to reduce the impedance of power distribution network (PDN) as low as possible up to high frequency range. In this paper, an on-chip power integrity evaluation system has been established using a test chip with both noise generating circuits and monitoring circuits for on-chip power supply noise. On-chip power integrity has been examined and compared for the cases with and without on-chip capacitance and for the various embedded capacitors inside an interposer.
KW - On-chip Power Integrity
KW - Power supply disturbance
KW - interposer
KW - power distribution network
KW - system-in-package
UR - http://www.scopus.com/inward/record.url?scp=84857007991&partnerID=8YFLogxK
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M3 - Conference contribution
AN - SCOPUS:84857007991
SN - 9789531841580
T3 - Proceedings of the 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits 2011, EMC COMPO 2011
SP - 165
EP - 169
BT - Proceedings of the 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits 2011, EMC COMPO 2011
T2 - 8th International Workshop on Electromagnetic Compatibility of Integrated Circuits, EMC COMPO 2011
Y2 - 6 November 2011 through 9 November 2011
ER -