TY - GEN
T1 - On-die PDN design and analysis for minimizing power supply noise
AU - Otsuka, Hiroki
AU - Kubo, Genki
AU - Kobayashi, Ryota
AU - Mido, Tatsuya
AU - Kobayashi, Yoshinori
AU - Fujii, Hideyuki
AU - Sudo, Toshio
PY - 2012/12/1
Y1 - 2012/12/1
N2 - Power integrity design is a critical issue for advanced CMOS LSIs which operate at higher clock frequency and at lower supply voltage. Power supply fluctuation excited by core circuits or I/O buffer circuits induces logic instability and electromagnetic radiation. Therefore, total impedance of power distribution network (PDN) must be designed as low as possible in the chip-package-board co-design. Especially, anti-resonance peaks in the PDN created by the parallel combination of on-chip capacitance and package inductance induce the unwanted power supply fluctuation. In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by adjusting different on-chip PDN properties. The simulated power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions. The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip.
AB - Power integrity design is a critical issue for advanced CMOS LSIs which operate at higher clock frequency and at lower supply voltage. Power supply fluctuation excited by core circuits or I/O buffer circuits induces logic instability and electromagnetic radiation. Therefore, total impedance of power distribution network (PDN) must be designed as low as possible in the chip-package-board co-design. Especially, anti-resonance peaks in the PDN created by the parallel combination of on-chip capacitance and package inductance induce the unwanted power supply fluctuation. In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by adjusting different on-chip PDN properties. The simulated power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions. The critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip.
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U2 - 10.1109/EDAPS.2012.6469418
DO - 10.1109/EDAPS.2012.6469418
M3 - Conference contribution
AN - SCOPUS:84875497740
SN - 9781467314435
T3 - 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012
SP - 17
EP - 20
BT - 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012
T2 - 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2012
Y2 - 9 December 2012 through 11 December 2012
ER -