TY - GEN
T1 - Optimal Design for Level-Shifter-Less Approach Using Channel Length Modulation Body Biasing
AU - Watanabe, Tatsuya
AU - Usami, Kimiyoshi
N1 - Funding Information:
This work was supported by VLSI Design and Education Center (VDEC) the University of Tokyo in collaboration with Synopsys. Inc.
Publisher Copyright:
© 2020 IEICE.
PY - 2020/7
Y1 - 2020/7
N2 - A multi-VDD design realizes LSIs to be low power by allowing to use multiple different power supply voltages. In this design, conversion of the voltage amplitude of the signal is necessary. This is usually done by inserting a circuit called a level shifter, between voltage domains as an interface. However, insertion of level shifter has disadvantages in silicon footprint, power consumption, and delays. In this paper, we propose a level-shifter-less approach by increasing channel length. We also propose the optimal design using both channel length modulation and body biasing.
AB - A multi-VDD design realizes LSIs to be low power by allowing to use multiple different power supply voltages. In this design, conversion of the voltage amplitude of the signal is necessary. This is usually done by inserting a circuit called a level shifter, between voltage domains as an interface. However, insertion of level shifter has disadvantages in silicon footprint, power consumption, and delays. In this paper, we propose a level-shifter-less approach by increasing channel length. We also propose the optimal design using both channel length modulation and body biasing.
KW - Body Biasing
KW - Channel Length Modulation
KW - Level-Shifter-Less
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M3 - Conference contribution
AN - SCOPUS:85091445905
T3 - ITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications
SP - 223
EP - 227
BT - ITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 35th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2020
Y2 - 3 July 2020 through 6 July 2020
ER -