TY - GEN
T1 - Power gating for FDSOI using dynamically body-biased power switch
AU - Kumagai, Yuichi
AU - Kudo, Masaru
AU - Usami, Kimiyoshi
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/3/18
Y1 - 2015/3/18
N2 - We propose a Dynamically Biased Multi Threshold CMOS (DBMT) technique for power gating in FDSOI. In DBMT, effective threshold voltage of a high-Vt power switch transistor is lowered by forward body biasing (FBB) to improve performance at the operation, while it is raised by reverse body biasing (RBB) to further reduce leakage in the sleep state. We applied this technique to a 32-bit multiplier circuit of an experimental CPU Geyser-1 in which the multiplier is power gated at run time in a fine-grained manner during the CPU operation [1]. Simulated results in 65nm FDSOI with thin BOX revealed that the area of the power switch (PS) in DBMT technique can be reduced by 55% as compared to the conventional MTCMOS when suppressing the delay increase due to PS insertion within 10%. DBMT reduces leakage energy of the multiplier considering the energy overhead by up to 55% as compared to the MTCMOS when running application programs.
AB - We propose a Dynamically Biased Multi Threshold CMOS (DBMT) technique for power gating in FDSOI. In DBMT, effective threshold voltage of a high-Vt power switch transistor is lowered by forward body biasing (FBB) to improve performance at the operation, while it is raised by reverse body biasing (RBB) to further reduce leakage in the sleep state. We applied this technique to a 32-bit multiplier circuit of an experimental CPU Geyser-1 in which the multiplier is power gated at run time in a fine-grained manner during the CPU operation [1]. Simulated results in 65nm FDSOI with thin BOX revealed that the area of the power switch (PS) in DBMT technique can be reduced by 55% as compared to the conventional MTCMOS when suppressing the delay increase due to PS insertion within 10%. DBMT reduces leakage energy of the multiplier considering the energy overhead by up to 55% as compared to the MTCMOS when running application programs.
KW - Body-Bias
KW - Low Power Technique
KW - Power Gating
KW - Sillicon-on-Thin-BOX MOSFET
UR - http://www.scopus.com/inward/record.url?scp=84926477192&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84926477192&partnerID=8YFLogxK
U2 - 10.1109/ULIS.2015.7063813
DO - 10.1109/ULIS.2015.7063813
M3 - Conference contribution
AN - SCOPUS:84926477192
T3 - EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon
SP - 221
EP - 224
BT - EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2015
Y2 - 26 January 2015 through 28 January 2015
ER -