Power supply noise suppression by optimizing on-die PDN impedance

Yoshinori Kobayashi; Ryota Kobayashi; Tatsuya Mido; Genki Kubo; Hiroki Otsuka; Hideyuki Fujii; Toshio Sudo

doi:10.1109/ICSJ.2012.6523443

Power supply noise suppression by optimizing on-die PDN impedance

Yoshinori Kobayashi, Ryota Kobayashi, Tatsuya Mido, Genki Kubo, Hiroki Otsuka, Hideyuki Fujii, Toshio Sudo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

Power integrity design has been becoming important in the advanced CMOS digital systems, because power supply noise induces logic instability and electromagnetic radiation. Especially, anti-resonance peaks in power distribution network (PDN) due to the chip-package interaction induce the unwanted power supply fluctuation, and result in large electromagnetic radiation. In this paper, effects of damping condition of the total PDN impedance on power supply noise have been studied by adding variable on-die RC circuit to the intrinsic on-die RC circuit in chip PDN. Two types of test chips were designed with different variable on-die PDN impedances. By varying the values of on-die RC circuit, the simulated waveforms of power supply noises for the two test chips have been changed from oscillatory region to damped regions.

Original language	English
Title of host publication	2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012
DOIs	https://doi.org/10.1109/ICSJ.2012.6523443
Publication status	Published - 2012 Dec 1
Event	2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012 - Kyoto, Japan Duration: 2012 Dec 10 → 2012 Dec 12

Publication series

Name	2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012

Conference

Conference	2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012
Country/Territory	Japan
City	Kyoto
Period	12/12/10 → 12/12/12

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ICSJ.2012.6523443

Cite this

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title = "Power supply noise suppression by optimizing on-die PDN impedance",

abstract = "Power integrity design has been becoming important in the advanced CMOS digital systems, because power supply noise induces logic instability and electromagnetic radiation. Especially, anti-resonance peaks in power distribution network (PDN) due to the chip-package interaction induce the unwanted power supply fluctuation, and result in large electromagnetic radiation. In this paper, effects of damping condition of the total PDN impedance on power supply noise have been studied by adding variable on-die RC circuit to the intrinsic on-die RC circuit in chip PDN. Two types of test chips were designed with different variable on-die PDN impedances. By varying the values of on-die RC circuit, the simulated waveforms of power supply noises for the two test chips have been changed from oscillatory region to damped regions.",

author = "Yoshinori Kobayashi and Ryota Kobayashi and Tatsuya Mido and Genki Kubo and Hiroki Otsuka and Hideyuki Fujii and Toshio Sudo",

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T1 - Power supply noise suppression by optimizing on-die PDN impedance

AU - Kobayashi, Yoshinori

AU - Kobayashi, Ryota

AU - Mido, Tatsuya

AU - Kubo, Genki

AU - Otsuka, Hiroki

AU - Fujii, Hideyuki

AU - Sudo, Toshio

PY - 2012/12/1

Y1 - 2012/12/1

N2 - Power integrity design has been becoming important in the advanced CMOS digital systems, because power supply noise induces logic instability and electromagnetic radiation. Especially, anti-resonance peaks in power distribution network (PDN) due to the chip-package interaction induce the unwanted power supply fluctuation, and result in large electromagnetic radiation. In this paper, effects of damping condition of the total PDN impedance on power supply noise have been studied by adding variable on-die RC circuit to the intrinsic on-die RC circuit in chip PDN. Two types of test chips were designed with different variable on-die PDN impedances. By varying the values of on-die RC circuit, the simulated waveforms of power supply noises for the two test chips have been changed from oscillatory region to damped regions.

AB - Power integrity design has been becoming important in the advanced CMOS digital systems, because power supply noise induces logic instability and electromagnetic radiation. Especially, anti-resonance peaks in power distribution network (PDN) due to the chip-package interaction induce the unwanted power supply fluctuation, and result in large electromagnetic radiation. In this paper, effects of damping condition of the total PDN impedance on power supply noise have been studied by adding variable on-die RC circuit to the intrinsic on-die RC circuit in chip PDN. Two types of test chips were designed with different variable on-die PDN impedances. By varying the values of on-die RC circuit, the simulated waveforms of power supply noises for the two test chips have been changed from oscillatory region to damped regions.

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Power supply noise suppression by optimizing on-die PDN impedance

Abstract

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