SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator

Nobuaki Ozaki; Kimiyoshi Usami; Hideharu Amano; Mitaro Namiki; Hiroshi Nakamura; Masaaki Kondo

doi:10.1109/COOLCHIPS.2011.5890918

SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator

Nobuaki Ozaki, Kimiyoshi Usami, Hideharu Amano, Mitaro Namiki, Hiroshi Nakamura, Masaaki Kondo

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

SLD(Silent Large Datapath)-1 is a prototype accelerator for media processing consisting of a large Processing Element (PE) array which includes 24bit 8 × 8 PEs with combinatorial circuits and a small micro-controller for data memory access. It was fabricated in 2.1mm 4.2mm × 65 nm CMOS, and achieves 1.356GOPS/11mW sustained performance by reducing overhead of clock tree and the benefit of voltage scaling.

Original language	English
Title of host publication	IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings
DOIs	https://doi.org/10.1109/COOLCHIPS.2011.5890918
Publication status	Published - 2011
Event	14th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XIV - Yokohama, Japan Duration: 2011 Apr 20 → 2011 Apr 22

Publication series

Name	IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings

Conference

Conference	14th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XIV
Country/Territory	Japan
City	Yokohama
Period	11/4/20 → 11/4/22

Keywords

65nmCMOS
Low Power
Reconfigurable System

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/COOLCHIPS.2011.5890918

Cite this

Ozaki, N., Usami, K., Amano, H., Namiki, M., Nakamura, H., & Kondo, M. (2011). SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator. In IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings Article 5890918 (IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings). https://doi.org/10.1109/COOLCHIPS.2011.5890918

SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator. / Ozaki, Nobuaki; Usami, Kimiyoshi; Amano, Hideharu et al.
IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings. 2011. 5890918 (IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ozaki, N, Usami, K, Amano, H, Namiki, M, Nakamura, H & Kondo, M 2011, SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator. in IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings., 5890918, IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings, 14th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XIV, Yokohama, Japan, 11/4/20. https://doi.org/10.1109/COOLCHIPS.2011.5890918

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SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator

Abstract

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Keywords

ASJC Scopus subject areas

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