Time-dependent dielectric breakdown characterization of 90- and 65-nm-Node Cu/SiOC interconnects with via plugs

Kazuyoshi Ueno, Akiko Kameyama, Akira Matsumoto, Manabu Iguchi, Toshiyuki Takewaki, Daisuke Oshida, Hironori Toyoshima, Naoyoshi Kawahara, Susumu Asada, Mieko Suzuki, Noriaki Oda

Research output: Contribution to journalArticlepeer-review

8 Citations (Scopus)


As the wiring-space decreases, the time-dependent dielectric breakdown (TDDB) of Cu/low-dielectric constant (k) interconnects becomes a critical reliability issue and more accurate prediction of the TDDB lifetime will be required. In this investigation, TDDB dependences on temperature and electric field are studied comprehensively for 90- and 65-nm-node Cu/ SiOC interconnects using practical multilevel test structures with via plugs. Low-electric-field TDDB tests down to 1 MV/cm. were carried out by a package TDDB method with high temperature up to 300°C. Linear dependence of the TDDB lifetime on the electric-field is observed down to 1 MV/cm, and this suggests that the lifetime can be predicted using the E-model. The linear dependence of the TDDB lifetime on temperature is also observed up to 300°C at 1.8 MV/cm. The activation energies for the 90 and 65 nm. nodes are almost the same values, 0.76 eV for the 90 nm node and 0.74 eV for the 65 nm node. Failure is observed at the interfaces between the cap dielectric (SiCN) and the silicon dioxide layer with a surface polished by chemical-mechanical polishing (CMP) for both nodes. It is noted that no difference in the failure modes is seen between dense SiOC for the 90 nm node and porous SiOC for the 65 nm node, in spite of the different materials used for the intermetal dielectrics. This suggests that the polished interfaces greatly affect on the TDDB lifetime for both nodes. Improved TDDB lifetime is obtained by increasing the post-CMP cleaning time and the pretreatment time before the cap dielectric deposition. Sufficient TDDB lifetimes of over 10 years under practical operating conditions are obtained for both 90- and 65-nm-node Cu/low-k interconnects with via plugs.

Original languageEnglish
Pages (from-to)1444-1451
Number of pages8
JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Issue number4 A
Publication statusPublished - 2007 Apr 5


  • Cu
  • Dielectric reliability
  • Interconnection
  • LSI
  • Low-k
  • Time-dependent dielectric breakdown

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)


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