TY - GEN
T1 - Tiny Two-Stage 1-GHz Time-Difference Amplifier without Input Time-Difference Limitation and Extreme Points
AU - Mamba, Atsushi
AU - Sasaki, Masahiro
N1 - Funding Information:
This work is supported by the VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Synopsys, Inc., Cadence Design Systems, Inc., Mentor Graphics, Inc., ROHM Corp., and Toppan Printing Corp.
Publisher Copyright:
© 2020 IEEE.
PY - 2020/11/23
Y1 - 2020/11/23
N2 - Conventional time-difference amplifiers (TDAs), which can improve the time-domain resolution, use capacitors and an external control circuit to make gain, control gain, and improve linearity. However, this configuration produces a limitation in the maximum operating frequency and high power consumption. This paper proposes and demonstrates a TDA for a variety of time-domain circuits. The proposed TDA consists of two circuits, including a modified SR latch circuit and gain control circuit (GCC). The linearity of this TDA is controlled by the GCC, which is a part of the amplifier, by only using the time-difference signals generated by the modified SR latch. This TDA is fabricated in the 0.18 J.1m CMOS process, and the core area occupies only 13 µm×14 µm. The measurement results show that the output time difference monotonically increases and has no extreme points for an entire clock period with a 1-GHz input clock. The gain of the flat region in the range of ±130 ps is 1.54 with a maximum gain error of less than 6.5%, and the power consumption is 2230 µW. The proposed TDA can be used for not only a time to digital converter, similar with conventional TDAs, but also circuits using the time domain, such as a high-speed comparators and time-difference adjustment methods.
AB - Conventional time-difference amplifiers (TDAs), which can improve the time-domain resolution, use capacitors and an external control circuit to make gain, control gain, and improve linearity. However, this configuration produces a limitation in the maximum operating frequency and high power consumption. This paper proposes and demonstrates a TDA for a variety of time-domain circuits. The proposed TDA consists of two circuits, including a modified SR latch circuit and gain control circuit (GCC). The linearity of this TDA is controlled by the GCC, which is a part of the amplifier, by only using the time-difference signals generated by the modified SR latch. This TDA is fabricated in the 0.18 J.1m CMOS process, and the core area occupies only 13 µm×14 µm. The measurement results show that the output time difference monotonically increases and has no extreme points for an entire clock period with a 1-GHz input clock. The gain of the flat region in the range of ±130 ps is 1.54 with a maximum gain error of less than 6.5%, and the power consumption is 2230 µW. The proposed TDA can be used for not only a time to digital converter, similar with conventional TDAs, but also circuits using the time domain, such as a high-speed comparators and time-difference adjustment methods.
KW - Linearity
KW - Metastability
KW - No extreme point transfer function
KW - Time domain
KW - Time-difference amplifier
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U2 - 10.1109/ICECS49266.2020.9294917
DO - 10.1109/ICECS49266.2020.9294917
M3 - Conference contribution
AN - SCOPUS:85099477957
T3 - ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings
BT - ICECS 2020 - 27th IEEE International Conference on Electronics, Circuits and Systems, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 27th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2020
Y2 - 23 November 2020 through 25 November 2020
ER -