Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating

Kimiyoshi Usami; Makoto Miyauchi; Masaru Kudo; Kazumitsu Takagi; Hideharu Amano; Mitaro Namiki; Masaaki Kondo; Hiroshi Nakamura

doi:10.1109/ISSOC.2014.6972438

Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating

Kimiyoshi Usami, Makoto Miyauchi, Masaru Kudo, Kazumitsu Takagi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper describes a new approach to reduce the ground bounce (GB) while keeping the wakeup time short for fine-grain power gating. We propose a novel algorithm to synthesize an optimal unbalanced buffer tree (UBT) that turns on parallel power switches with slight time differences. We have applied our algorithm to function units of a 32-bit microprocessor. Experimental results have revealed that our UBT gives better solution than the conventional daisy-chain approach in the space of wakeup time and GB. For example, in the ALU, our UBT suppressed the maximum GB voltage to 16mV which is 24% smaller than that of the parallel daisy chain, while keeping the wakeup time 0.6ns. In the 32b×32b multiplier, our UBT suppressed GB by 32% lower than the daisy chain but still kept the wakeup time 0.7ns. The microprocessor test chip with our UBT technique is successfully under operation.

Original language	English
Title of host publication	2014 International Symposium on System-on-Chip, SoC 2014
Editors	Jari Nurmi, Peeter Ellervee, Dragomir Milojevic, Ondrej Daniel, Tommi Paakki
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479968909
DOIs	https://doi.org/10.1109/ISSOC.2014.6972438
Publication status	Published - 2014 Dec 2
Event	2014 16th International Symposium on System-on-Chip, SoC 2014 - Tampere, Finland Duration: 2014 Oct 28 → 2014 Oct 29

Publication series

Name	2014 International Symposium on System-on-Chip, SoC 2014

Conference

Conference	2014 16th International Symposium on System-on-Chip, SoC 2014
Country/Territory	Finland
City	Tampere
Period	14/10/28 → 14/10/29

Keywords

ground bounce
low power
power gating

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISSOC.2014.6972438

Cite this

Usami, K., Miyauchi, M., Kudo, M., Takagi, K., Amano, H., Namiki, M., Kondo, M., & Nakamura, H. (2014). Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. In J. Nurmi, P. Ellervee, D. Milojevic, O. Daniel, & T. Paakki (Eds.), 2014 International Symposium on System-on-Chip, SoC 2014 [6972438] (2014 International Symposium on System-on-Chip, SoC 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSOC.2014.6972438

Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. / Usami, Kimiyoshi; Miyauchi, Makoto; Kudo, Masaru et al.
2014 International Symposium on System-on-Chip, SoC 2014. ed. / Jari Nurmi; Peeter Ellervee; Dragomir Milojevic; Ondrej Daniel; Tommi Paakki. Institute of Electrical and Electronics Engineers Inc., 2014. 6972438 (2014 International Symposium on System-on-Chip, SoC 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Usami, K, Miyauchi, M, Kudo, M, Takagi, K, Amano, H, Namiki, M, Kondo, M & Nakamura, H 2014, Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. in J Nurmi, P Ellervee, D Milojevic, O Daniel & T Paakki (eds), 2014 International Symposium on System-on-Chip, SoC 2014., 6972438, 2014 International Symposium on System-on-Chip, SoC 2014, Institute of Electrical and Electronics Engineers Inc., 2014 16th International Symposium on System-on-Chip, SoC 2014, Tampere, Finland, 14/10/28. https://doi.org/10.1109/ISSOC.2014.6972438

Usami K, Miyauchi M, Kudo M, Takagi K, Amano H, Namiki M et al. Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. In Nurmi J, Ellervee P, Milojevic D, Daniel O, Paakki T, editors, 2014 International Symposium on System-on-Chip, SoC 2014. Institute of Electrical and Electronics Engineers Inc. 2014. 6972438. (2014 International Symposium on System-on-Chip, SoC 2014). doi: 10.1109/ISSOC.2014.6972438

Usami, Kimiyoshi ; Miyauchi, Makoto ; Kudo, Masaru et al. / Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. 2014 International Symposium on System-on-Chip, SoC 2014. editor / Jari Nurmi ; Peeter Ellervee ; Dragomir Milojevic ; Ondrej Daniel ; Tommi Paakki. Institute of Electrical and Electronics Engineers Inc., 2014. (2014 International Symposium on System-on-Chip, SoC 2014).

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AB - This paper describes a new approach to reduce the ground bounce (GB) while keeping the wakeup time short for fine-grain power gating. We propose a novel algorithm to synthesize an optimal unbalanced buffer tree (UBT) that turns on parallel power switches with slight time differences. We have applied our algorithm to function units of a 32-bit microprocessor. Experimental results have revealed that our UBT gives better solution than the conventional daisy-chain approach in the space of wakeup time and GB. For example, in the ALU, our UBT suppressed the maximum GB voltage to 16mV which is 24% smaller than that of the parallel daisy chain, while keeping the wakeup time 0.6ns. In the 32b×32b multiplier, our UBT suppressed GB by 32% lower than the daisy chain but still kept the wakeup time 0.7ns. The microprocessor test chip with our UBT technique is successfully under operation.

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Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating

Abstract

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Keywords

ASJC Scopus subject areas

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