Kimiyoshi Usami

2023

A 200mV Operable On-Chip Temperature Sensor for IoT Devices Powered by Energy Harvesters with Ultra-Low Output Voltage

Usami, K., Wang, S., Nagai, K., Latronico, G. & Mele, P., 2023, Proceedings of 2023 IEEE International Conference on Internet of Things and Intelligence Systems, IoTaIS 2023. Institute of Electrical and Electronics Engineers Inc., p. 65-71 7 p. (Proceedings of 2023 IEEE International Conference on Internet of Things and Intelligence Systems, IoTaIS 2023).

研究成果: Conference contribution

1 被引用数 (Scopus)

A 40 nm 2 kb MTJ-Based Non-Volatile SRAM Macro with Novel Data-Aware Store Architecture for Normally Off Computing

Suzuki, K., Hiraga, K., Bessho, K., Usami, K. & Umebayashi, T., 2023, 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023. Institute of Electrical and Electronics Engineers Inc., (Digest of Technical Papers - Symposium on VLSI Technology; vol. 2023-June).

研究成果: Conference contribution

Design Optimization of Leakage Based PUF Circuit targeting at Ultra-Low Voltage Operation

Hata, S. & Usami, K., 2023, 2023 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2023. Institute of Electrical and Electronics Engineers Inc., (2023 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2023).

研究成果: Conference contribution

1 被引用数 (Scopus)

Thermal coupling analysis and improved dynamic temperature control algorithm for 3D-LSI

Wang, S. & Usami, K., 2023, 2023 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2023. Institute of Electrical and Electronics Engineers Inc., (2023 International Technical Conference on Circuits/Systems, Computers, and Communications, ITC-CSCC 2023).

研究成果: Conference contribution

2022

Optimal switching time to minimize store energy in MTJ-based flip-flops under process and temperature variations

Usami, K., Yokoyama, D., Kamei, A. & Amano, H., 2022, 2022 IEEE Nordic Circuits and Systems Conference, NORCAS 2022 - Proceedings. Nurmi, J., Wisland, D. T., Aunet, S. & Kjelgaard, K. (eds.). Institute of Electrical and Electronics Engineers Inc., (2022 IEEE Nordic Circuits and Systems Conference, NORCAS 2022 - Proceedings).

研究成果: Conference contribution

2 被引用数 (Scopus)

Thermal Transient Analysis and Dynamic Temperature Control Algorithm for 3-D Stacked Chips

Wang, S. & Usami, K., 2022, ITC-CSCC 2022 - 37th International Technical Conference on Circuits/Systems, Computers and Communications. Institute of Electrical and Electronics Engineers Inc., p. 614-617 4 p. (ITC-CSCC 2022 - 37th International Technical Conference on Circuits/Systems, Computers and Communications).

研究成果: Conference contribution

1 被引用数 (Scopus)

2021

Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops

Kamei, A., Kojima, T., Amano, H., Yokoyama, D., Miyauchi, H., Usami, K., Hiraga, K., Suzuki, K. & Bessho, K., 2021, Proceedings - 2021 IEEE 14th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2021. Institute of Electrical and Electronics Engineers Inc., p. 273-280 8 p. (Proceedings - 2021 IEEE 14th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2021).

研究成果: Conference contribution

7 被引用数 (Scopus)

2020

Approximate Computing based on Latest-result Reuse for Image Edge Detection

Usami, K., Ochi, H. & Ono, Y., 2020 7月, ITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications. Institute of Electrical and Electronics Engineers Inc., p. 234-239 6 p. 9182998. (ITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications).

研究成果: Conference contribution

2 被引用数 (Scopus)

Energy Efficient Approximate Storing of Image Data for MTJ Based Non-volatile Memory

Ono, Y. & Usami, K., 2020 8月, Proceedings - 9th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2020. Institute of Electrical and Electronics Engineers Inc., 9188231. (Proceedings - 9th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2020).

研究成果: Conference contribution

2 被引用数 (Scopus)

Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization

Usami, K., Akiba, S., Amano, H., Ikezoe, T., Hiraga, K., Suzuki, K. & Kanda, Y., 2020 4月, IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 9097630. (IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings).

研究成果: Conference contribution

5 被引用数 (Scopus)

Optimal Design for Level-Shifter-Less Approach Using Channel Length Modulation Body Biasing

Watanabe, T. & Usami, K., 2020 7月, ITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications. Institute of Electrical and Electronics Engineers Inc., p. 223-227 5 p. 9182820. (ITC-CSCC 2020 - 35th International Technical Conference on Circuits/Systems, Computers and Communications).

研究成果: Conference contribution

2019

Approximate Computing Technique Using Memoization and Simplified Multiplication

Ono, Y. & Usami, K., 2019 6月, 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019. Institute of Electrical and Electronics Engineers Inc., 8793369. (34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019).

研究成果: Conference contribution

3 被引用数 (Scopus)

Level-Shifter-Less Approach for Multi-V_DD SoC Design to Employ Body Bias Control in FD-SOI

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R. & Amano, H., 2019, VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things - 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Revised and Extended Selected Papers. Maniatakos, M., Elfadel, I. A. M., Sonza Reorda, M., Ugurdag, H. F., Monteiro, J. & Reis, R. (eds.). Springer New York LLC, p. 1-21 21 p. (IFIP Advances in Information and Communication Technology; vol. 500).

研究成果: Conference contribution

Single Supply Level Shifter Circuit using body-bias

Takeyoshi, Y. & Usami, K., 2019 6月, 34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019. Institute of Electrical and Electronics Engineers Inc., 8793384. (34th International Technical Conference on Circuits/Systems, Computers and Communications, ITC-CSCC 2019).

研究成果: Conference contribution

3 被引用数 (Scopus)

2018

A coarse grained-reconfigurable accelerator with energy efficient MTJ-based non-volatile flip-flops

Ikezoe, T., Amano, H., Akaike, J., Usami, K., Kudo, M., Hiraga, K., Shuto, Y. & Yagami, K., 2018 7月 2, 2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018. Andrews, D., Cumplido, R., Feregrino, C. & Stroobandt, D. (eds.). Institute of Electrical and Electronics Engineers Inc., 8641712. (2018 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2018).

研究成果: Conference contribution

7 被引用数 (Scopus)

Building block multi-chip systems using inductive coupling through chip interface

Amano, H., Kuroda, T., Nakamura, H., Usami, K., Kondo, M., Matsutani, H. & Namiki, M., 2018 5月 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 152-154 3 p. (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

研究成果: Conference contribution

Digital embedded memory scheme using voltage scaling and body bias separation for low-power system

Yoshida, Y., Usami, K. & Amano, H., 2018 5月 29, Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., p. 148-149 2 p. (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

研究成果: Conference contribution

1 被引用数 (Scopus)

Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application

Usami, K., Akaike, J., Akiba, S., Kudo, M., Amano, H., Ikezoe, T., Hiraga, K., Shuto, Y. & Yagami, K., 2018 11月 15, Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018. Institute of Electrical and Electronics Engineers Inc., p. 91-98 8 p. 8537701. (Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018).

研究成果: Conference contribution

13 被引用数 (Scopus)

2017

Design and implementation methodology of energy-efficient Standard Cell Memory with optimized Body-Bias separation in Silicon-on-Thin-BOX

Yoshida, Y. & Usami, K., 2017 6月 29, Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings. Nassiopoulou, A. G. & Sarafis, P. (eds.). Institute of Electrical and Electronics Engineers Inc., p. 43-46 4 p. 7962596. (Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 - Proceedings).

研究成果: Conference contribution

1 被引用数 (Scopus)

Level-shifter free approach for multi-V_dd SOTB employing adaptive Vt modulation for pMOSFET

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R. & Amano, H., 2017 7月 2, 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. Institute of Electrical and Electronics Engineers Inc., p. 1-3 3 p. (2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017; vol. 2018-March).

研究成果: Conference contribution

2 被引用数 (Scopus)

Level-shifter-less approach for multi-V _DD design to use body bias control in FD-SOI

Usami, K., Kogure, S., Yoshida, Y., Magasaki, R. & Amano, H., 2017 12月 13, 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings. IEEE Computer Society, 8203473. (IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC).

研究成果: Conference contribution

1 被引用数 (Scopus)

Nonvolatile power gating with MTJ based nonvolatile flip-flops for a microprocessor

Kudo, M. & Usami, K., 2017 10月 10, NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium. Institute of Electrical and Electronics Engineers Inc., 8064472. (NVMSA 2017 - 6th IEEE Non-Volatile Memory Systems and Applications Symposium).

研究成果: Conference contribution

9 被引用数 (Scopus)

2015

A leakage current monitor circuit using silicon on thin BOX MOSFET for dynamic back gate bias control

Okuhara, H., Usami, K. & Amano, H., 2015 7月 14, IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XVIII - Proceedings. Institute of Electrical and Electronics Engineers Inc., 7158656. (IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XVIII - Proceedings).

研究成果: Conference contribution

An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET

Okuhara, H., Kitamori, K., Fujita, Y., Usami, K. & Amano, H., 2015 9月 21, Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2015. Institute of Electrical and Electronics Engineers Inc., p. 207-212 6 p. 7273515. (Proceedings of the International Symposium on Low Power Electronics and Design; vol. 2015-September).

研究成果: Conference contribution

13 被引用数 (Scopus)

Measurement of the minimum energy point in Silicon on Thin-BOX(SOTB) and bulk MOSFET

Nakamura, S., Kawasaki, J., Kumagai, Y. & Usami, K., 2015 3月 18, EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon. Institute of Electrical and Electronics Engineers Inc., p. 193-196 4 p. 7063746. (EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon).

研究成果: Conference contribution

13 被引用数 (Scopus)

Power gating for FDSOI using dynamically body-biased power switch

Kumagai, Y., Kudo, M. & Usami, K., 2015 3月 18, EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon. Institute of Electrical and Electronics Engineers Inc., p. 221-224 4 p. 7063813. (EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon).

研究成果: Conference contribution

2014

A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode

Kamohara, S., Sugii, N., Ishibashi, K., Usami, K., Amano, H., Kobayashi, K. & Pham, C. K., 2014 5月 25, 2014 IEEE Hot Chips 26 Symposium, HCS 2014. Institute of Electrical and Electronics Engineers Inc., 7478838. (2014 IEEE Hot Chips 26 Symposium, HCS 2014).

研究成果: Conference contribution

1 被引用数 (Scopus)

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

Ishibashi, K., Sugii, N., Usami, K., Amano, H., Kobayashi, K., Pham, C. K., Makiyama, H., Yamamoto, Y., Shinohara, H., Iwamatsu, T., Yamaguchi, Y., Oda, H., Hasegawa, T., Okanishi, S., Yanagita, H., Kamohara, S., Kadoshima, M., Maekawa, K., Yamashita, T. & Le, D. H. & 5 others, Yomogita, T., Kudo, M., Kitamori, K., Kondo, S. & Manzawa, Y., 2014, IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII. IEEE Computer Society, 6842954. (IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2014 IEEE COOL Chips XVII).

研究成果: Conference contribution

23 被引用数 (Scopus)

A thermal management system for building block computing systems

Fujita, Y., Usami, K. & Amano, H., 2014 11月 6, Proceedings - 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014. Institute of Electrical and Electronics Engineers Inc., p. 165-171 7 p. 6949468. (Proceedings - 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2014).

研究成果: Conference contribution

2 被引用数 (Scopus)

Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors

Usami, K., Kudo, M., Matsunaga, K., Kosaka, T., Tsurui, Y., Wang, W., Amano, H., Kobayashi, H., Sakamoto, R., Namiki, M., Kondo, M. & Nakamura, H., 2014, 2014 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014 - Proceedings. p. 843-848 6 p. 6742995. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: Conference contribution

9 被引用数 (Scopus)

Design and evaluation of fine-grained power-gating for embedded microprocessors

Kondo, M., Kobyashi, H., Sakamoto, R., Wada, M., Tsukamoto, J., Namiki, M., Wang, W., Amano, H., Matsunaga, K., Kudo, M., Usami, K., Komoda, T. & Nakamura, H., 2014, Proceedings - Design, Automation and Test in Europe, DATE 2014. Institute of Electrical and Electronics Engineers Inc., 6800359. (Proceedings -Design, Automation and Test in Europe, DATE).

研究成果: Conference contribution

17 被引用数 (Scopus)

Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era

Kamohara, S., Sugii, N., Yamamoto, Y., Makiyama, H., Yamashita, T., Hasegawa, T., Okanishi, S., Yanagita, H., Kadoshima, M., Maekawa, K., Mitani, H., Yamagata, Y., Oda, H., Yamaguchi, Y., Ishibashi, K., Amano, H., Usami, K., Kobayashi, K., Mizutani, T. & Hiramoto, T., 2014 9月 8, Digest of Technical Papers - Symposium on VLSI Technology. Institute of Electrical and Electronics Engineers Inc., 6894413. (Digest of Technical Papers - Symposium on VLSI Technology).

研究成果: Conference contribution

9 被引用数 (Scopus)

Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating

Usami, K., Miyauchi, M., Kudo, M., Takagi, K., Amano, H., Namiki, M., Kondo, M. & Nakamura, H., 2014 12月 2, 2014 International Symposium on System-on-Chip, SoC 2014. Nurmi, J., Ellervee, P., Milojevic, D., Daniel, O. & Paakki, T. (eds.). Institute of Electrical and Electronics Engineers Inc., 6972438. (2014 International Symposium on System-on-Chip, SoC 2014).

研究成果: Conference contribution

1 被引用数 (Scopus)

2013

An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages

Abe, S. Y., Shi, Y., Usami, K., Yanagisawa, M. & Togawa, N., 2013, 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013. 6533808. (2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013).

研究成果: Conference contribution

A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface

Miura, N., Koizumi, Y., Sasaki, E., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013 5月 24, 2013 IEEE Hot Chips 25 Symposium, HCS 2013. Institute of Electrical and Electronics Engineers Inc., 7478328. (2013 IEEE Hot Chips 25 Symposium, HCS 2013).

研究成果: Conference contribution

A scalable 3D heterogeneous multi-core processor with inductive-coupling ThruChip interface

Miura, N., Koizumi, Y., Sasaki, E., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013, IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI. 6547916. (IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI).

研究成果: Conference contribution

2 被引用数 (Scopus)

2012

A multi-Vdd dynamic variable-pipeline on-chip router for CMPs

Matsutani, H., Hirata, Y., Koibuchi, M., Usami, K., Nakamura, H. & Amano, H., 2012, ASP-DAC 2012 - 17th Asia and South Pacific Design Automation Conference. p. 407-412 6 p. 6164982. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: Conference contribution

16 被引用数 (Scopus)

CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect

Koizumi, Y., Sasaki, E., Amano, H., Matsutani, H., Take, Y., Kuroda, T., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2012, Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012. p. 543-546 4 p. 6339375. (Proceedings - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012).

研究成果: Conference contribution

6 被引用数 (Scopus)

Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect

Koizumi, Y., Amano, H., Matsutani, H., Miura, N., Kuroda, T., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2012, FPT 2012 - 2012 International Conference on Field-Programmable Technology. p. 293-296 4 p. 6412150. (FPT 2012 - 2012 International Conference on Field-Programmable Technology).

研究成果: Conference contribution

7 被引用数 (Scopus)

Efficient leakage power saving by sleep depth controlling for multi-mode power gating

Takeda, S., Miwa, S., Usami, K. & Nakamura, H., 2012, Proceedings of the 13th International Symposium on Quality Electronic Design, ISQED 2012. p. 625-632 8 p. 6187558. (Proceedings - International Symposium on Quality Electronic Design, ISQED).

研究成果: Conference contribution

4 被引用数 (Scopus)

Stepwise sleep depth control for run-time leakage power saving

Takeda, S., Miwa, S., Usami, K. & Nakamura, H., 2012, GLSVLSI'12 - Proceedings of the Great Lakes Symposium on VLSI 2012. p. 233-238 6 p. (Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI).

研究成果: Conference contribution

2 被引用数 (Scopus)

Trade-off analysis of fine-grained power gating methods for functional units in a CPU

Wang, W., Ohta, Y., Ishii, Y., Usami, K. & Amano, H., 2012, Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV. 6216587. (Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV).

研究成果: Conference contribution

7 被引用数 (Scopus)

2011

A 2.72GOPS/11mW low power reconfigurable accelerator with a highly parallel datapath consisting of combinatorial circuits in 65nm CMOS

Ozaki, N., Yasuda, Y., Saito, Y., Ikebuchi, D., Kimura, M., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011, 2011 International Symposium on Integrated Circuits, ISIC 2011. p. 579-584 6 p. 6131929. (2011 International Symposium on Integrated Circuits, ISIC 2011).

研究成果: Conference contribution

Cool mega-array: A highly energy efficient reconfigurable accelerator

Ozaki, N., Yoshihiro, Y., Saito, Y., Ikebuchi, D., Kimura, M., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011, 2011 International Conference on Field-Programmable Technology, FPT 2011. 6132668. (2011 International Conference on Field-Programmable Technology, FPT 2011).

研究成果: Conference contribution

16 被引用数 (Scopus)

Dynamic V_DD switching technique and mapping optimization in dynamically reconfigurable processor for efficient energy reduction

Yamamoto, T., Hironaka, K., Hayakawa, Y., Kimura, M., Amano, H. & Usami, K., 2011, Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Proceedings. p. 230-241 12 p. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 6578 LNCS).

研究成果: Conference contribution

9 被引用数 (Scopus)

Geyser-2: The second prototype CPU with fine-grained run-time power gating

Zhao, L., Ikebuchi, D., Saito, Y., Kamata, M., Seki, N., Kojima, Y., Amano, H., Koyama, S., Hashida, T., Umahashi, Y., Masuda, D., Usami, K., Kimura, K., Namiki, M., Takeda, S., Nakamura, H. & Kondo, M., 2011, 2011 16th Asia and South Pacific Design Automation Conference, ASP-DAC 2011. p. 87-88 2 p. 5722310. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: Conference contribution

11 被引用数 (Scopus)

On-chip detection methodology for break-even time of power gated function units

Usami, K., Goto, Y., Matsunaga, K., Koyama, S., Ikebuchi, D., Amano, H. & Nakamura, H., 2011, IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011. p. 241-246 6 p. 5993643. (Proceedings of the International Symposium on Low Power Electronics and Design).

研究成果: Conference contribution

18 被引用数 (Scopus)

SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator

Ozaki, N., Usami, K., Amano, H., Namiki, M., Nakamura, H. & Kondo, M., 2011, IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings. 5890918. (IEEE Symposium on Low-Power and High-Speed Chips - 2011 IEEE COOL Chips XIV, Proceedings).

研究成果: Conference contribution

2 被引用数 (Scopus)

2010

Adaptive power gating for function units in a microprocessor

Usami, K., Hashida, T., Koyama, S., Yamamoto, T., Ikebuchi, D., Amano, H., Namiki, M., Kondo, M. & Nakamura, H., 2010, Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010. p. 29-37 9 p. 5450407. (Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010).

研究成果: Conference contribution

7 被引用数 (Scopus)

Geyser-1: A MIPS R3000 CPU core with fine-grained run-time power gating

Ikebuchi, D., Seki, N., Kojima, Y., Kamata, M., Zhao, L., Amano, H., Shirai, T., Koyama, S., Hashida, T., Umahashi, Y., Masuda, H., Usami, K., Takeda, S., Nakamura, H., Namiki, M. & Kondo, M., 2010, 2010 15th Asia and South Pacific Design Automation Conference, ASP-DAC 2010. p. 369-370 2 p. 5419857. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

研究成果: Conference contribution

5 被引用数 (Scopus)

宇佐美 公良

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宇佐美公良