宇佐美 公良

研究成果

年別の研究成果 1987 1998 2008 2009 2011 2012 2013 2014 2015 2023

• 58 Conference contribution
• 36 Article
• 10 Conference article
• 8 Paper
• 3 その他
  • 2 Editorial
  • 1 Chapter

年別の研究成果

年別の研究成果

検索結果

• 2023

  A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops

  Kamei, A., Amano, H., Kojima, T., Yokoyama, D., Usami, K., Hiraga, K., Suzuki, K. & Bessho, K., 2023, (Accepted/In press) In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. p. 1-11 11 p.

  研究成果: Article › 査読

  • Tunnel junctions 100%
  • Flip flop circuits 82%
  • Electron energy levels 27%
  • Normal distribution 26%
  • Particle accelerators 24%
• 2021

  Energy Efficient Approximate Storing of Image Data for MTJ Based Non-Volatile Flip-Flops and MRAM

  Ono, Y. & Usami, K., 2021 7月 1, In: IEICE Transactions on Electronics. 7, p. 338-349 12 p.

  研究成果: Article › 査読

  • Flip flop circuits 100%
  • Image quality 63%
  • Data storage equipment 52%
  • Energy 40%
  • Statistical Models 15%
• 2017

  Energy-efficient standard cell memory with optimized body-bias separation in Silicon-on-Thin-BOX (SOTB)

  Yoshida, Y. & Usami, K., 2017 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E100A, 12, p. 2785-2796 12 p.

  研究成果: Article › 査読

  • Energy Efficient 100%
  • Silicon 86%
  • Cell 45%
  • Data storage equipment 37%
  • Standards 33%
  2 被引用数 (Scopus)

• Power Optimization Methodology for Ultralow Power Microcontroller with Silicon on Thin BOX MOSFET

  Okuhara, H., Fujita, Y., Usami, K. & Amano, H., 2017 4月, In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25, 4, p. 1578-1582 5 p., 7802624.

  研究成果: Article › 査読

  • Microcontrollers 100%
  • Silicon 80%
  • Bias voltage 42%
  • Temperature 41%
  • Electric potential 17%
  15 被引用数 (Scopus)
• 2016

  An operating system guided fine-grained power gating control based on runtime characteristics of applications

  Koshiba, A., Sato, M., Usami, K., Amano, H., Sakamoto, R., Kondo, M., Nakamura, H. & Namiki, M., 2016 8月, In: IEICE Transactions on Electronics. E99C, 8, p. 926-935 10 p.

  研究成果: Article › 査読

  • Electric power utilization 100%
  • Application programs 81%
  • Networks (circuits) 49%
  • Application 42%
  • Block Like Crystal 36%

• Multi-voltage variable pipeline routers with the same clock frequency for low-power network-on-chips systems

  Ahmed, A. B., Matsutani, H., Koibuchi, M., Usami, K. & Amano, H., 2016 8月 1, In: IEICE Transactions on Electronics. E99C, 8, p. 909-917 9 p.

  研究成果: Article › 査読

  • Pipeline 100%
  • Network-on-chip 96%
  • Routers 82%
  • Clocks 73%
  • Pipelines 65%
  2 被引用数 (Scopus)
• 2015

  A fine-grained power gating control on linux monitoring power consumption of processor functional units

  Koshiba, A., Wada, M., Sakamoto, R., Sato, M., Kosaka, T., Usami, K., Amano, H., Kondo, M., Nakamura, H. & Namiki, M., 2015 7月 1, In: IEICE Transactions on Electronics. E98C, 7, p. 559-568 10 p.

  研究成果: Article › 査読

  • Linux 100%
  • Electric power utilization 71%
  • Monitoring 54%
  • Voltage 46%
  • Energy 45%
  3 被引用数 (Scopus)

• An energy-efficient floorplan driven high-level synthesis algorithm for multiple clock domains design

  Abe, S. Y., Shi, Y., Usami, K., Yanagisawa, M. & Togawa, N., 2015 7月 1, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E98A, 7, p. 1376-1391 16 p.

  研究成果: Article › 査読

  • High-level Synthesis 100%
  • Energy Efficient 82%
  • High level synthesis 64%
  • Clocks 43%
  • Design 31%
  1 被引用数 (Scopus)

• A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode

  Ishibashi, K., Sugii, N., Kamohara, S., Usami, K., Amano, H., Kobayashi, K. & Pham, C. K., 2015 7月 1, In: IEICE Transactions on Electronics. E98C, 7, p. 536-543 8 p.

  研究成果: Article › 査読

  • Sleep 100%
  • Program processors 79%
  • Voltage 68%
  • Energy 44%
  • Wearable computers 35%
  18 被引用数 (Scopus)
• 2013

  A scalable 3D heterogeneous multicore with an inductive ThruChip interface

  Miura, N., Koizumi, Y., Take, Y., Matsutani, H., Kuroda, T., Amano, H., Sakamoto, R., Namiki, M., Usami, K., Kondo, M. & Nakamura, H., 2013 11月 1, In: IEEE Micro. 33, 6, p. 6-15 10 p., 6684194.

  研究成果: Article › 査読

  • Particle accelerators 100%
  • Linux 51%
  • Program processors 41%
  • Costs 37%
  • Energy utilization 34%
  26 被引用数 (Scopus)

• Fine-grained run-tume power gating through co-optimization of circuit, architecture, and system software design

  Nakamura, H., Wang, W., Ohta, Y., Usami, K., Amano, H., Kondo, M. & Namiki, M., 2013 4月, In: IEICE Transactions on Electronics. E96-C, 4, p. 404-412 9 p.

  研究成果: Article › 査読

  • Software design 100%
  • Networks (circuits) 53%
  • Reduction 44%
  • Electric power utilization 42%
  • Power control 35%

• Floorplan driven architecture and high-level synthesis algorithm for dynamic multiple supply voltages

  Abe, S. Y., Shi, Y., Usami, K., Yanagisawa, M. & Togawa, N., 2013 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E96-A, 12, p. 2597-2611 15 p.

  研究成果: Article › 査読

  • High-level Synthesis 100%
  • High level synthesis 64%
  • Voltage 57%
  • Architecture 56%
  • Floorplanning 29%
  2 被引用数 (Scopus)
• 2011

  Cool mega-arrays: Ultralow-power reconfigurable accelerator chips

  Ozaki, N., Yasuda, Y., Izawa, M., Saito, Y., Ikebuchi, D., Amano, H., Nakamura, H., Usami, K., Namiki, M. & Kondo, M., 2011 11月 1, In: IEEE Micro. 31, 6, p. 6-18 13 p., 6060791.

  研究成果: Article › 査読

  • Particle accelerators 100%
  • Data flow graphs 70%
  • Data storage equipment 60%
  • Microcontrollers 48%
  • Information management 45%
  48 被引用数 (Scopus)

• Design and implementation fine-grained power gating on microprocessor functional units

  Lei, Z., Ikebuchi, D., Usami, K., Namiki, M., Kondo, M., Nakamura, H. & Amano, H., 2011, In: IPSJ Transactions on System LSI Design Methodology. 4, p. 182-192 11 p.

  研究成果: Article › 査読

  • Microprocessor chips 100%
  • Electric power utilization 40%
  4 被引用数 (Scopus)

• Geyser-2: The Second Prototype CPU with Fine-grained Run-time Power Gating

  Zhao, L., Ikebuchi, D., Saito, Y., Kamata, M., Seki, N., Kojima, Y., Amano, H., Koyama, S., Hashida, T., Umahashi, Y., Masuda, D., Usami, K., Kimura, K., Namiki, M., Takeda, S., Nakamura, H. & Kondo, M., 2011 1月 26, In: 16th Asia and South Pacific Design Automation Conference (ASP-DAC) 2011. p. 87-88

  研究成果: Article › 査読

  11 被引用数 (Scopus)

• Performance, area, and power evaluations of ultrafine-grained run-time power-gating routers for CMPs

  Matsutani, H., Koibuchi, M., Ikebuchi, D., Usami, K., Nakamura, H. & Amano, H., 2011 4月, In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 4, p. 520-533 14 p., 5737865.

  研究成果: Article › 査読

  • Routers 100%
  • Network-on-chip 19%
  • Application programs 15%
  • Communication 8%
  34 被引用数 (Scopus)

• Sleep transistor sizing method using accurate delay estimation considering input vector pattern and non-linear current model

  Takeda, S., Kim, K., Nakamura, H. & Usami, K., 2011 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E94-A, 12, p. 2499-2509 11 p.

  研究成果: Article › 査読

  • Delay Estimation 100%
  • Sleep 77%
  • Transistors 44%
  • Leakage 19%
  • Model 17%
  1 被引用数 (Scopus)
• 2010

  Circuit Structure of Level Shifter for Sub-threshold Operation

  Ishizaki, T. & Usami, K., 2010 7月 6, In: 25th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'10).

  研究成果: Article › 査読

• Geyser-1: A MIPS R3000 CPU core with fine-grained run-time power gating

  D.Ikebuchi, D. I., N.Seki, N. S., Y.Kojima, Y. K., M.Kamata, M. K., L.Zhao, L. Z., H.Amano, H. A., T.Shirai, T. S., S.Koyama, S. K., T.Hashida, T. H., Y.Umahashi, Y. U., H.Masuda, H. M., K.Usami, K. U., S.Takeda, S. T., H.Nakamura, H. N., M.Namiki, M. N., M.Kondo, M. K. & Usami, K., 2010 1月 18, In: Default journal. p. 369-370

  研究成果: Article › 査読

  5 被引用数 (Scopus)
• 2009

  Effectiveness of Power Gating for a Superscalar processor

  Muto, T. & Usami, K., 2009 7月 7, In: The 24th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'09). p. 420-423

  研究成果: Article › 査読

  17 被引用数 (Scopus)

• Geyser-1: A MIPS R3000 CPU core with Fine Grain Runtime Power Gating

  D.Ikebuchi, D. I., N.Seki, N. S., Y.Kojima, Y. K., M.Kamata, M. K., L.Zhao, L. Z., H.Amano, H. A., T.Shirai, T. S., S.Koyama, S. K., T.Hashida, T. H., Y.Umahashi, Y. U., H.Masuda, H. M., K.Usami, K. U., S.Takeda, S. T., H.Nakamura, H. N., M.Namiki, M. N., M.Kondo, M. K. & Usami, K., 2009 11月 16, In: IEEE Asian Solid-State Circuits Conference (A-SSCC) 2009. p. 281-284

  研究成果: Article › 査読

  33 被引用数 (Scopus)
• 2008

  Design and Analysis of On-chip Leakage Monitor using an MTCMOS circuit

  Koyama, S., Takeda, S. & Usami, K., 2008 7月 8, In: The 23rd International Technical Conference on Circuits/Systems; Computers and Communications (ITC-CSCC'08). p. 205-208

  研究成果: Article › 査読

• Power Gating for Ultra-low Leakage: Physics; Design; and Analysis

  F.Jerry, F. J., K.Choi, K. C., K.Usami, K. U. & Usami, K., 2008 3月 3, In: Design; Automation and Test in Europe 2008 (DATE'08).

  研究成果: Article › 査読

• Power Reduction Technique for Dynamic Reconfigurable Processors with Dynamic Assignment of Dual Supply Voltages

  Umahashi, Y., Kambayashi, Y., Kato, M., Hasegawa, Y., Amano, H. & Usami, K., 2008 7月 8, In: The 23rd International Technical Conference on Circuits/Systems; Computers and Communications (ITC-CSCC'08). p. 213-216

  研究成果: Article › 査読

• Power-Switch Clustering Method for Static Timing Analysis

  T.Hashida, T. H., K.Usami, K. U. & Usami, K., 2008 7月 8, In: 23rd International Technical Conference on Circuits/Systems; Computers and Communications (ITC-CSCC'08). p. 217-220

  研究成果: Article › 査読
• 2006

  Delay modeling and critical-path delay calculation for MTCMOS circuits

  Ohkubo, N. & Usami, K., 2006 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E89-A, 12, p. 3482-3490 9 p.

  研究成果: Article › 査読

  • Critical Path 100%
  • Delay circuits 86%
  • Modeling 40%
  • Networks (circuits) 34%
  • SPICE 33%

• Leakage in Nanometer CMOS Technologies -Methodologies for Power Gating

  Usami, K., Sakurai, T. & authors., . M., 2006 10月 1, In: Default journal. p. 77-104

  研究成果: Article › 査読
• 2005

  Analysis on MTCMOS Circuits based on Lumped RC Model for Virtual Ground Line

  K.Usami, K. U., N.Ohkubo, N. O., M.Shirakawa, M. S. & Usami, K., 2005 10月 1, In: IEEE International SoC Design Conference 2005 (ISOCC'05). p. 116-119

  研究成果: Article › 査読
• 2004

  Dynamic sleep control for finite-state-machines to reduce active leakage power

  Usami, K. & Yoshioka, H., 2004 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E87-A, 12, p. 3116-3123 8 p.

  研究成果: Article › 査読

  • Sleep 100%
  • Finite State Machine 89%
  • Leakage 88%
  • Finite automata 73%
  • Transistors 57%
  5 被引用数 (Scopus)
• 2002

  Code coverage-based power estimation techniques for microprocessors

  Qu, G., Kawabe, N., Usami, K. & Potkonjak, M., 2002 10月, In: Journal of Circuits, Systems and Computers. 11, 5, p. 557-574 18 p.

  研究成果: Article › 査読

  • Microprocessor chips 100%
  • Embedded software 69%
  • Energy dissipation 23%
  • Simulators 20%
  • Energy utilization 19%
  4 被引用数 (Scopus)

• Selective multi-threshold technique for high-performance and low-standby applications

  Usami, K., Kawabe, N., Koizumi, M., Seta, K. & Furusawa, T., 2002 12月, In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E85-A, 12, p. 2667-2673 7 p.

  研究成果: Article › 査読

  • High Performance 100%
  • Code division multiple access 72%
  • Transistors 65%
  • Cell 56%
  • WCDMA 53%
  1 被引用数 (Scopus)
• 2000

  Function-level power estimation methodology for microprocessors

  Qu, G., Kawabe, N., Usami, K. & Potkonjak, M., 2000 1月 1, In: Proceedings-Design Automation Conference. p. 810-813 4 p.

  研究成果: Article › 査読

  • Microprocessor chips 100%
  • Embedded software 92%
  • Energy dissipation 31%
  • Simulators 26%
  • Energy utilization 26%
  70 被引用数 (Scopus)
• 1998

  A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme

  Takahashi, M., Hamada, M., Nishikawa, T., Arakida, H., Fujita, T., Hatori, F., Mita, S., Suzuki, K., Chiba, A., Terazawa, T., Sano, F., Watanabe, Y., Usami, K., Igarashi, M., Ishikawa, T., Kanazawa, M., Kuroda, T. & Furuyama, T., 1998 11月, In: IEEE Journal of Solid-State Circuits. 33, 11, p. 1772-1778 7 p.

  研究成果: Article › 査読

  • Voltage scaling 100%
  • Energy dissipation 68%
  • Static random access storage 44%
  • Electric potential 41%
  • Transistors 34%
  73 被引用数 (Scopus)

• Automated low-power technique exploiting multiple supply voltages applied to a media processor

  Usami, K., Igarashi, M., Minami, F., Ishikawa, T., Kanazawa, M., Ichida, M. & Nogami, K., 1998 3月 1, In: IEEE Journal of Solid-State Circuits. 33, 3, p. 463-472 10 p.

  研究成果: Article › 査読

  • Electric potential 100%
  • Clocks 82%
  212 被引用数 (Scopus)
• 1991

  Hierarchical Symbolic Design Methodology for Large-Scale Data Paths

  Usami, K., Sugeno, Y., Matsumoto, N. & Mori, S., 1991 3月, In: IEEE Journal of Solid-State Circuits. 26, 3, p. 381-385 5 p.

  研究成果: Article › 査読

  • Turnaround time 100%
  • Adders 86%
  • Masks 74%
  • Microprocessor chips 71%
  • Transistors 67%
• 1989

  Design of a 32-bit Microprocessor, TX1

  Tokumaru, T., Masuda, E., Usami, K., Miyata, M., Iwamura, J. & Hori, C., 1989 8月, In: IEEE Journal of Solid-State Circuits. 24, 4, p. 938-944 7 p.

  研究成果: Article › 査読

  • Microprocessor chips 100%
  • Design for testability 51%
  • Transistors 31%
  • Clocks 31%
  • Metals 23%
  1 被引用数 (Scopus)