TY - JOUR
T1 - 110Gb/s multiplexing and demultiplexing ICs
AU - Suzuki, Yasuyuki
AU - Amamiya, Yasushi
AU - Yamazaki, Zin
AU - Wada, Shigeki
AU - Uchida, Hiroaki
AU - Kurioka, Chiharu
AU - Tanaka, Shinichi
AU - Hida, Hikaru
PY - 2003
Y1 - 2003
N2 - A 120Gb/s multiplexer and a 110Gb/s demultiplexer are implemented in an InP HBT process. They feature a direct drive series-gating configuration selector, an asymmetrical latch flip-flop, and broadband impedance matching with inverted micro-strip lines. Their input sensitivity is less than 100mVpp, and the output swing is more than 400mVpp.
AB - A 120Gb/s multiplexer and a 110Gb/s demultiplexer are implemented in an InP HBT process. They feature a direct drive series-gating configuration selector, an asymmetrical latch flip-flop, and broadband impedance matching with inverted micro-strip lines. Their input sensitivity is less than 100mVpp, and the output swing is more than 400mVpp.
UR - http://www.scopus.com/inward/record.url?scp=2442703020&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=2442703020&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:2442703020
SN - 0193-6530
VL - 47
SP - 182-183+518
JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
T2 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference: Visuals Supplement
Y2 - 15 February 2003 through 19 February 2003
ER -