A 40 nm 2 kb MTJ-Based Non-Volatile SRAM Macro with Novel Data-Aware Store Architecture for Normally Off Computing

Kenta Suzuki, Keizo Hiraga, Kazuhiro Bessho, Kimiyoshi Usami, Taku Umebayashi

研究成果: Conference contribution

抄録

We propose a magnetic tunnel junction (MTJ)-based nonvolatile SRAM (NVSRAM) to obtain normally off computing. The proposed NVSRAM not only combines SRAM performance and non-volatility but also shows improved area efficiency by sharing the driver with peripheral circuits. Moreover, the data-aware store scheme enables reduction in store energy by data comparison control and a verify operation that mitigates MTJ process variation. We fabricated a 2 kb macro by using a 40 nm process with optimized memory cells to overcome the risk of latch destruction of conventional cells. The measurement results demonstrated a non-volatile function and 3.5x store energy reduction by the store control optimization.

本文言語English
ホスト出版物のタイトル2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN(電子版)9784863488069
DOI
出版ステータスPublished - 2023
イベント2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023 - Kyoto, Japan
継続期間: 2023 6月 112023 6月 16

出版物シリーズ

名前Digest of Technical Papers - Symposium on VLSI Technology
2023-June
ISSN(印刷版)0743-1562

Conference

Conference2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
国/地域Japan
CityKyoto
Period23/6/1123/6/16

ASJC Scopus subject areas

  • 電子工学および電気工学

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