TY - GEN
T1 - A 40 nm 2 kb MTJ-Based Non-Volatile SRAM Macro with Novel Data-Aware Store Architecture for Normally Off Computing
AU - Suzuki, Kenta
AU - Hiraga, Keizo
AU - Bessho, Kazuhiro
AU - Usami, Kimiyoshi
AU - Umebayashi, Taku
N1 - Publisher Copyright:
© 2023 JSAP.
PY - 2023
Y1 - 2023
N2 - We propose a magnetic tunnel junction (MTJ)-based nonvolatile SRAM (NVSRAM) to obtain normally off computing. The proposed NVSRAM not only combines SRAM performance and non-volatility but also shows improved area efficiency by sharing the driver with peripheral circuits. Moreover, the data-aware store scheme enables reduction in store energy by data comparison control and a verify operation that mitigates MTJ process variation. We fabricated a 2 kb macro by using a 40 nm process with optimized memory cells to overcome the risk of latch destruction of conventional cells. The measurement results demonstrated a non-volatile function and 3.5x store energy reduction by the store control optimization.
AB - We propose a magnetic tunnel junction (MTJ)-based nonvolatile SRAM (NVSRAM) to obtain normally off computing. The proposed NVSRAM not only combines SRAM performance and non-volatility but also shows improved area efficiency by sharing the driver with peripheral circuits. Moreover, the data-aware store scheme enables reduction in store energy by data comparison control and a verify operation that mitigates MTJ process variation. We fabricated a 2 kb macro by using a 40 nm process with optimized memory cells to overcome the risk of latch destruction of conventional cells. The measurement results demonstrated a non-volatile function and 3.5x store energy reduction by the store control optimization.
KW - MTJ
KW - Non-volatile SRAM
KW - Non-volatile flip-flop
KW - Normally off computing
KW - Power gating
KW - STT-MRAM
UR - http://www.scopus.com/inward/record.url?scp=85167609000&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85167609000&partnerID=8YFLogxK
U2 - 10.23919/VLSITechnologyandCir57934.2023.10185432
DO - 10.23919/VLSITechnologyandCir57934.2023.10185432
M3 - Conference contribution
AN - SCOPUS:85167609000
T3 - Digest of Technical Papers - Symposium on VLSI Technology
BT - 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2023 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2023
Y2 - 11 June 2023 through 16 June 2023
ER -