抄録
A robust embedded ladder-oxide {k = 2.9)/copper (Cu) multilevel interconnect is demonstrated for 0.13 μm complementary metal oxide semiconductor (CMOS) generation. A stable ladder-oxide intermetal dielectric (IMD) is integrated by the Cu metallization with a minimum wiring pitch of 0.34 μm, and a single damascene (S/D) Cu-plug structure is applied. An 18% reduction in wiring capacitance is obtained compared with that in SiO 2 IMDs. The superior controllability of metal thickness by the S/D process enables us to enhance the MPU maximum frequency easily. The stress-migration lifetime of vias on wide metals for the S/D Cu-plug structure is longer than that for a dual damascene (D/D) structure. Reliability test results such as electromigration (EM), the temperature dependant dielectric breakdown (TDDB) of Cu interconnects, and pressure cooker test (PCT) results are acceptable. Moreover, a high flexibility in a thermal design is obtained.
本文言語 | English |
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ページ(範囲) | 954-961 |
ページ数 | 8 |
ジャーナル | Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers |
巻 | 46 |
号 | 3 A |
DOI | |
出版ステータス | Published - 2007 3月 8 |
ASJC Scopus subject areas
- 工学(全般)
- 物理学および天文学(全般)