A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13 μm complementary metal oxide semiconductor generation

Noriaki Oda, Shinya Ito, Toshiyuki Takewaki, Kazutoshi Shiba, Hiroyuki Kunishima, Nobuo Hironaga, Ichiro Honma, Hiroaki Nanba, Shinji Yokogawa, Akiko Kameyama, Takayuki Goto, Tatsuya Usami, Koichi Ohto, Akira Kubo, Mieko Suzuki, Yoshiaki Yamamoto, Susumu Watanabe, Kenta Yamada, Masahiro Ikeda, Kazuyoshi UenoTadahiko Horiuchi

研究成果: Article査読

9 被引用数 (Scopus)

抄録

A robust embedded ladder-oxide {k = 2.9)/copper (Cu) multilevel interconnect is demonstrated for 0.13 μm complementary metal oxide semiconductor (CMOS) generation. A stable ladder-oxide intermetal dielectric (IMD) is integrated by the Cu metallization with a minimum wiring pitch of 0.34 μm, and a single damascene (S/D) Cu-plug structure is applied. An 18% reduction in wiring capacitance is obtained compared with that in SiO 2 IMDs. The superior controllability of metal thickness by the S/D process enables us to enhance the MPU maximum frequency easily. The stress-migration lifetime of vias on wide metals for the S/D Cu-plug structure is longer than that for a dual damascene (D/D) structure. Reliability test results such as electromigration (EM), the temperature dependant dielectric breakdown (TDDB) of Cu interconnects, and pressure cooker test (PCT) results are acceptable. Moreover, a high flexibility in a thermal design is obtained.

本文言語English
ページ(範囲)954-961
ページ数8
ジャーナルJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
46
3 A
DOI
出版ステータスPublished - 2007 3月 8

ASJC Scopus subject areas

  • 工学(全般)
  • 物理学および天文学(全般)

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