A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13um complementary metal oxide semiconductor generation

N. Oda; S. Ito; T. Takewaki; K. Shiba; H. Kunishima; N. Hironaga; I. Honma; H. Nanba; S. Yokogawa; A. Kameyama; T. Goto; T. Usami; K. Ohto; A. Kubo; M. Suzuki; Y. Yamamoto; S. Watanabe; K. Yamada; M. Ikeda; K. Ueno;T. Horiuchi; Kazuyoshi Ueno

A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13um complementary metal oxide semiconductor generation

N. Oda, S. Ito, T. Takewaki, K. Shiba, H. Kunishima, N. Hironaga, I. Honma, H. Nanba, S. Yokogawa, A. Kameyama, T. Goto, T. Usami, K. Ohto, A. Kubo, M. Suzuki, Y. Yamamoto, S. Watanabe, K. Yamada, M. Ikeda, K. Ueno;T. HoriuchiKazuyoshi Ueno

機能制御システム専攻

研究成果: Article › 査読

6 被引用数 (Scopus)

本文言語	English
ページ（範囲）	954-961
ジャーナル	Japanese Journal of Applied Physics
巻	46
出版ステータス	Published - 2007 3月 5

引用スタイル

Oda, N., Ito, S., Takewaki, T., Shiba, K., Kunishima, H., Hironaga, N., Honma, I., Nanba, H., Yokogawa, S., Kameyama, A., Goto, T., Usami, T., Ohto, K., Kubo, A., Suzuki, M., Yamamoto, Y., Watanabe, S., Yamada, K., Ikeda, M., ... Ueno, K. (2007). A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13um complementary metal oxide semiconductor generation. Japanese Journal of Applied Physics, 46, 954-961.

Oda, N, Ito, S, Takewaki, T, Shiba, K, Kunishima, H, Hironaga, N, Honma, I, Nanba, H, Yokogawa, S, Kameyama, A, Goto, T, Usami, T, Ohto, K, Kubo, A, Suzuki, M, Yamamoto, Y, Watanabe, S, Yamada, K, Ikeda, M, Horiuchi, KUT & Ueno, K 2007, 'A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13um complementary metal oxide semiconductor generation', Japanese Journal of Applied Physics, vol. 46, pp. 954-961.

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title = "A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13um complementary metal oxide semiconductor generation",

author = "N. Oda and S. Ito and T. Takewaki and K. Shiba and H. Kunishima and N. Hironaga and I. Honma and H. Nanba and S. Yokogawa and A. Kameyama and T. Goto and T. Usami and K. Ohto and A. Kubo and M. Suzuki and Y. Yamamoto and S. Watanabe and K. Yamada and M. Ikeda and Horiuchi, {K. Ueno;T.} and Kazuyoshi Ueno",

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language = "English",

volume = "46",

pages = "954--961",

journal = "Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes",

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TY - JOUR

T1 - A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13um complementary metal oxide semiconductor generation

AU - Oda, N.

AU - Ito, S.

AU - Takewaki, T.

AU - Shiba, K.

AU - Kunishima, H.

AU - Hironaga, N.

AU - Honma, I.

AU - Nanba, H.

AU - Yokogawa, S.

AU - Kameyama, A.

AU - Goto, T.

AU - Usami, T.

AU - Ohto, K.

AU - Kubo, A.

AU - Suzuki, M.

AU - Yamamoto, Y.

AU - Watanabe, S.

AU - Yamada, K.

AU - Ikeda, M.

AU - Horiuchi, K. Ueno;T.

AU - Ueno, Kazuyoshi

PY - 2007/3/5

Y1 - 2007/3/5

M3 - Article

SN - 0021-4922

VL - 46

SP - 954

EP - 961

JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

ER -