An 820 Pin PGA for Ultralarge-Scale BiCMOS Devices

Yoichi Hiruta, Naohiko Hirano, Toshio Sudo

研究成果: Article査読

9 被引用数 (Scopus)


A high pin count and high performance PGA has been developed for next-generation ASIC devices which apply half-micron BiCMOS technology and have a maximum usable gate count of 300k. This new package has been designed with due consideration of all package functions, electrical, thermal, and mechanical. A surface mount type pin joint was adopted to realize a high wiring density of the printed wiring board. This package has 820 pins with a 50 mil pitch, and 5 rows. A highly accurate tape automated bonding (TAB) technology was applied to the die assembly to achieve the narrow pitch and high pad count of the bonding between the die and the package. The thermal resistance from the die to the ambient is lower than. 1.5°C/W at 1 m/s air flow velocity. The electrical parameters of the package were quantified. The measured cutoff frequency (−3 dB) was kept at 1.25 GHz including the TAB lead. The electrical characteristics of the package have realized a complete transmitted signal form above 50 MHz. The high reliability of the package and surface mount type soldering has been confirmed from temperature-cycling tests and fatigue life estimation.

ジャーナルIEEE Transactions on Components, Hybrids, and Manufacturing Technology
出版ステータスPublished - 1993 12月

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 工学(全般)
  • 産業および生産工学
  • 電子工学および電気工学


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